Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	ONSO3305US - Onsemi346	The method also includes forming an isolation/passivation layer over each of the plurality of semiconductor die. The isolation layer is formed over the first side and the sidewalls of each of the plurality of semiconductor die. In various implementations, the isolation layer may extend to the one or more dams between the semiconductor die and the optically transmissive substrate. In some implementations, the isolation layer may include, by non-limiting example, aluminum oxide, silicon dioxide, silicon nitride, aluminum nitride, and other dielectric materials. Referring to FIG. 13, each of the plurality of semiconductor die are illustrated after formation of the isolation layer.	61	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	The method of forming semiconductor packages without TSVs also includes singulating the semiconductor die and a metal layer 56 remaining after etching the semiconductor wafer. Referring to FIG. 10, the layer of oxide and metal layers is labeled element 56. Referring to FIG. 11, the plurality of die is illustrated after singulation of those layers. Singulating through the semiconductor die and metal layer exposes inner terminals 58 of the first RDL 32 on the optically permissive substrate 24. In various implementations, one or more inner terminals may be exposed after singulating. Singulation may be performed through laser cutting, sawing, etching, or other methods capable of severing semiconductor material and metal layers. Referring to FIG. 12, an enlarged view of the inner terminals 58 of the first RDL 32 is illustrated after singulation of the metal layers.	60	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Each of the two or more die pads may have a pad pitch of substantially 70 microns.	28	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	The method also includes thinning the semiconductor wafer 36 on the first side 38 of the semiconductor wafer. In various implementations, the wafer may be thinned through, by non-limiting example, mechanical grinding, chemical mechanical polishing (CMP), wet etching, atmospheric downstream plasma (ADP), dry chemical etching (DCE), or other methods of decreasing the thickness of a semiconductor wafer. Referring to FIG. 9, the semiconductor wafer 36 coupled to the optically transmissive substrate 24 after thinning of the semiconductor wafer is illustrated.	58	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	The method also includes coupling the second side of the semiconductor wafer to the first side of the optically transmissive substrate. Referring to FIG. 7, the semiconductor wafer 36 is illustrated coupled to the optically transmissive lid 24. As illustrated, the inner bumps are coupled to the optically transmissive lid 24 on either side of the scribe line. Referring to FIG. 8, an enlargement of area A in FIG. 7 is illustrated. In FIG. 8, the interconnection of the inner bump 46 with the first RDL 32 is illustrated. The inner bump 46 provides the mechanical and electrical coupling between the die pad 44 and the first RDL 32. As illustrated in this particular implementation, the inner bump includes two metal layers. In this implementations, the inner bump includes a copper pillar 48 with a solder tip 50. In various implementations, the die pad pitch may be about 70 microns. In other implementations, the inner bump may include only one metallic material such as a solder. In some implementations, the die pad pitch may be about 60 microns. The size of the pad pitch in semiconductor packages formed using the method described herein is smaller than semiconductor packages using TSVs which can have a pad pitch larger than 200 microns.	57	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Referring to FIG. 6, an implementation of a semiconductor wafer 36 is illustrated. The semiconductor wafer 36 has a first side 38 and a second side 40. The semiconductor wafer includes a plurality of active areas 42 on the second side of the semiconductor wafer. As illustrated, two die pads 44 are visible on either side of each of the plurality of active areas. In some implementations, more than two die pads may be positioned around each of the plurality of active areas. The method of forming semiconductor packages includes forming inner bumps on each of the die pads. The inner bumps may include conductive materials, such as by non-limiting example, solder and copper. Referring to FIG. 6, the semiconductor wafer 36 is illustrated after formation of the inner bumps 46 on the die pads 44.	56	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	In various implementations, the method may include forming dams on the optically transmissive substrate. Referring to FIG. 5, one or more dams 34 are illustrated after formation over a portion of the first RDLs 32. In various implementations, the dams may be formed of material including, by non-limiting example, liquid epoxy, silicone, or other encapsulants that may provide device protection, reduce warpage, demonstrate excellent flow, offer good adhesion to multiple substrates, and/or have the strength to handle over-molding and subsequent process steps. In some implementations, adhesive or other material may be formed over the first RDLs on the first side of the optically transmissive substrate 24.	55	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Referring to FIG. 4, a top view of an optically transmissive substrate 24 is illustrated. A method of forming a semiconductor package may include providing an optically transmissive substrate. Various methods of manufacturing semiconductor packages as described herein may be used including wafer level processes and panel level processes. Panel level processes may have cost and productivity advantages. Panel level processing may allow for parallel processing of more units of semiconductor packages in a given period compared with wafer level processes without the waste of having to process partial die that can occur in wafer level processing. Only a portion of a panel or substrate is illustrated in the following figures but it is understood that the processing continues for each of the various packages included in the remainder of the panel. The optically transmissive substrate includes a first side and a second side as illustrated in FIG. 3. The method includes forming a first redistribution layer (RDL) on a first side of the optically transmissive substrate over one of more scribe lines on the first side of the optically transmissive substrate. The first RDLs are illustrated over the scribe lines in both FIGS. 3 and 4. On the outer edges of the optically transmissive substrate, fragments of the first RDLs are illustrated because only a portion of a panel or substrate is illustrated in the following figures.	54	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Referring to FIG. 3, a side view of an implementation of an optically transmissive substrate is illustrated. In various implementations, the optically transmissive substrate may include, by non-limiting example, glass, polycarbonate, acrylic, plastics, or other materials that allow some or all of a desired wavelength of light to pass through the material. The optically transmissive substrate has a first side 28 and a second side 26. The scribe lines 30 are illustrated on the first side of the optically transmissive substrate in FIG. 3. However, the scribe lines 30 may be visible from either the first side or the second side of the optically transmissive lid. The scribe lines 30 on the optically transmissive substrate may be thinner in methods of forming a semiconductor package having no TSVs as described herein in comparison to methods of forming semiconductor packages having TSVs. By non-limiting example, the scribe lines illustrated may have a thickness of less than 150 microns.	53	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Referring again to FIG. 1, the semiconductor device includes a passivation layer 13 around the edges and first side of the semiconductor die. In various implementations, the passivation layer may include, by non-limiting example, aluminum oxide, silicon dioxide, silicon nitride, aluminum nitride, and other dielectric materials that have good adhesion, are chemically inert, and/or corrosion resistant. As illustrated, the semiconductor package also includes solder balls 15 coupled to the first side of the semiconductor die. In various implementations, different surface mount interconnects such as pillars or stud bumps may be used. In some implementations, the interconnects may be formed of copper, solder, alloys thereof, or other electrically conductive materials.	52	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Referring to FIG. 2, an expanded view of the interconnect bumps 14, first RDL 16, and second RDL 18 is illustrated. The two bumps 14 are coupled to two die pads or metal pads 20 on either side of the active area of the device. In various implementations, there may be two or more bumps coupled to two or more die pads. The two bumps 14 are coupled with the first RDL 16 to provide mechanical and electrical connection between die pads 20 on the second side of the semiconductor die and a second RDL 18 that is electrically coupled with outer terminals 22 on the first side 6 of the semiconductor die 4. The use of interconnection bumps and two RDLs eliminates the need to form through silicon vias (TSVs) through the semiconductor die material itself. The formation of TSVs can cause thermal and mechanical stress to the semiconductor die. TSV formation can also cause damage to the die pad including cracks and over etching of the pads. Die pad damage can account for most of the failures in current TSV-type image sensor chip scale packages (CSP). The use of interconnect bumps and multiple RDLs may also enable the use of pad pitches that are smaller than 200 microns. For example, semiconductor packages with interconnect bumps may have pad pitches of about 60 microns. In some implementations, the pad pitch may be about 70 microns where the interconnection bumps are copper pillar bumps. In various implementations, the copper pillar bumps may have solder tips. In other implementations, the interconnect bumps may be solder balls.	51	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Referring to FIG. 1, an implementation of a semiconductor package 2 is illustrated. The package 2 includes a semiconductor die 4 having a first side 6 and a second side 8. The semiconductor die is an image sensor die having an active area 10 on the second side 8 of the die 4. As illustrated, the sidewalls of the semiconductor die are angled. In various implementations, the angles of the sidewalls may be between 85 degrees and 60 degrees. The angles of the sidewalls may be formed through etching. In some implementations, the etching may be dry etching or wet etching. In various implementations, the semiconductor die may be a different device than an image sensor, such as, by non-limiting example, a processor, a microcontroller, a power semiconductor device, or any other semiconductor device type. An optically transmissive lid 12 is coupled to the semiconductor die 4 through an adhesive, two interconnect bumps 14, and a first redistribution layer (RDL) 16. In various implementations, the optically transmissive lid may include, by non-limiting example, glass, polycarbonate, acrylic, plastics, or other materials that allow some or all of a desired wavelength of light to pass through the material. In various implementations, the adhesive may include, by non-limiting example, epoxy, resin, polymers, glue, and other adhesive materials used in coupling components of semiconductor devices. In other implementations, one or more dams may be coupled between the semiconductor die and the optically transmissive lid.	50	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Each of the two or more die pads may have a pad pitch of substantially 60 microns.	27	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	1.Technical Field	2	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Aspects of this document relate generally to semiconductor packages, such as image sensor packages for use in cameras, cell phones, and similar devices. More specific implementations involve image sensor chip scale packages.	3	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Background	4	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Semiconductor packages sometimes have through silicon vias (TSVs) to provide electrical interconnection between front side metal pads and backside outer terminals of an image sensor package. Formation of TSVs includes silicon and dielectric etch, isolation lithography, as well as temperature changes during the processing steps.	5	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die.	6	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Implementations of semiconductor packages may include one, all, or any of the following:	7	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	A pad pitch of the two or more bumps may be substantially 60 microns.	8	Added by DJM 3 2021	3/3/21, 12:00 AM

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