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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
51
Application Number
16455676
Reference Case 1
Reference Case 2
Content
Referring to FIG. 2, an expanded view of the interconnect bumps 14, first RDL 16, and second RDL 18 is illustrated. The two bumps 14 are coupled to two die pads or metal pads 20 on either side of the active area of the device. In various implementations, there may be two or more bumps coupled to two or more die pads. The two bumps 14 are coupled with the first RDL 16 to provide mechanical and electrical connection between die pads 20 on the second side of the semiconductor die and a second RDL 18 that is electrically coupled with outer terminals 22 on the first side 6 of the semiconductor die 4. The use of interconnection bumps and two RDLs eliminates the need to form through silicon vias (TSVs) through the semiconductor die material itself. The formation of TSVs can cause thermal and mechanical stress to the semiconductor die. TSV formation can also cause damage to the die pad including cracks and over etching of the pads. Die pad damage can account for most of the failures in current TSV-type image sensor chip scale packages (CSP). The use of interconnect bumps and multiple RDLs may also enable the use of pad pitches that are smaller than 200 microns. For example, semiconductor packages with interconnect bumps may have pad pitches of about 60 microns. In some implementations, the pad pitch may be about 70 microns where the interconnection bumps are copper pillar bumps. In various implementations, the copper pillar bumps may have solder tips. In other implementations, the interconnect bumps may be solder balls.
Notes
Added by DJM 3 2021
Raw Data
<w:p w14:paraId="548EFD34" w14:textId="4FBD29ED" w:rsidR="006B59B0" w:rsidRPr="007D1539" w:rsidRDefault="001026B2" w:rsidP="007D1539"><w:pPr><w:numPr><w:ilvl w:val="0"/><w:numId w:val="7"/></w:numPr><w:overflowPunct w:val="0"/><w:autoSpaceDE w:val="0"/><w:autoSpaceDN w:val="0"/><w:adjustRightInd w:val="0"/><w:spacing w:line="480" w:lineRule="auto"/><w:rPr><w:szCs w:val="24"/></w:rPr></w:pPr><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">Referring to FIG. 2, an expanded </w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">view of the interconnect bumps 14, first RDL 16, and second RDL 18 is illustrated. The two bumps 14 are coupled to </w:t></w:r><w:r w:rsidR="001B6397" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">two </w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">die pads or metal pads 20 on either side of the active area of the device. </w:t></w:r><w:r w:rsidR="001B6397" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">In various implementations, there may be two or more bumps coupled to two or more die pads. </w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">The two bumps 14 are coupled with the first RDL 16 to provide </w:t></w:r><w:r w:rsidR="001B6397" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">mechanical and </w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">electrical connection between die pads 20 on the second side of the semiconductor die and a second </w:t></w:r><w:r w:rsidR="00995A02"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>RDL</w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 18 that is electrically coupled with outer terminals 22 on the first side </w:t></w:r><w:r w:rsidR="001B6397" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">6 </w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>of the semiconductor die</w:t></w:r><w:r w:rsidR="001B6397" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 4</w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">. The use of interconnection bumps and two RDLs eliminates the need to form through silicon </w:t></w:r><w:proofErr w:type="spellStart"/><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>vias</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> (TSVs) through the semiconductor die material</w:t></w:r><w:r w:rsidR="00E42EEC"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> itself</w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">. The formation of TSVs can cause thermal and mechanical stress to the semiconductor die. TSV formation can also cause damage to the die pad including cracks and over etching of the </w:t></w:r><w:r w:rsidR="001B6397" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>pads. Die pad damage</w:t></w:r><w:r w:rsidR="00E42EEC"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> can</w:t></w:r><w:r w:rsidR="006B59B0" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> </w:t></w:r><w:r w:rsidR="00313975" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">account for most of the failures in current TSV-type image sensor chip scale packages (CSP). </w:t></w:r><w:r w:rsidR="006B59B0" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">The use of interconnect bumps and </w:t></w:r><w:r w:rsidR="001B6397" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>multiple</w:t></w:r><w:r w:rsidR="006B59B0" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> RDLs may also enable the use of pad pitches that are smaller than 200 microns. For example, semiconductor packages with interconnect bumps may have pad pitches of </w:t></w:r><w:r w:rsidR="00E42EEC"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>about</w:t></w:r><w:r w:rsidR="006B59B0" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 60 microns. In some implementations, the pad pitch may be</w:t></w:r><w:r w:rsidR="00E42EEC"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> about</w:t></w:r><w:r w:rsidR="006B59B0" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 70 microns where the interconnect</w:t></w:r><w:r w:rsidR="001B6397" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>ion bumps</w:t></w:r><w:r w:rsidR="006B59B0" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> are copper pillar bumps. In various implementations, the </w:t></w:r><w:r w:rsidR="006B59B0" w:rsidRPr="007D1539"><w:rPr><w:szCs w:val="24"/></w:rPr><w:lastRenderedPageBreak/><w:t xml:space="preserve">copper pillar bumps may have solder tips. In other implementations, the interconnect bumps may be solder balls. </w:t></w:r></w:p>
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