Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	US-8380915-A1	Each data structure is stored as one or more packets. Each data structure may have one or more container packets. Each packet contains a header. The header may include a header type field. Type fields may include data, attribute, metadata, data segment delimiters (multi-packet), data structures, data linkages, and the like. The header may also include information regarding the size of the packet, such as the number of bytes of data included in the packet. The length of the packet may be established by the packet type. The header may include information that establishes the relationship of the packet to a data structure. An example might be the use of an offset in a data packet header to identify the location of the data segment within the data structure. One of skill in the art will recognize other information that may be included in a header added to data by a packetizer 302 and other information that may be added to a data packet.	97	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In a read, modify, write operation, data packets associated with requested data are located and read in a read operation. Data segments of the modified requested data that have been modified are not written to the location from which they are read. Instead, the modified data segments are again converted to data packets and then written sequentially to the next available location in the logical page currently being written. The index entries for the respective data packets are modified to point to the packets that contain the modified data segments. The entry or entries in the index for data packets associated with the same requested data that have not been modified will include pointers to original location of the unmodified data packets. Thus, if the original requested data is maintained, for example to maintain a previous version of the requested data, the original requested data will have pointers in the index to all data packets as originally written. The new requested data will have pointers in the index to some of the original data packets and pointers to the modified data packets in the logical page that is currently being written.	68	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Write Data Pipeline	95	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The solid-state storage controller 104 may also include control and status registers 340 and control queues 342, a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350. The solid-state storage controller 104, in the depicted embodiment, includes a configuration module 352 that may be part of the write data pipeline 106 and/or part of the read data pipeline 108, or may be independent from the write data pipeline 106 and the read data pipeline 108. The components of the solid-state controller 104 and associated write data pipeline 106 and read data pipeline 108 are described below. In other embodiments, synchronous solid-state storage media 110 may be used and synchronization buffers 308328 may be eliminated.	94	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	FIG. 3A is a schematic block diagram illustrating one embodiment 300 of a solid-state storage controller 104 with a write data pipeline 106 and a read data pipeline 108 in a solid-state storage device 102 in accordance with the present invention. The embodiment 300 includes a data bus 204, a local bus 206, and buffer control 208, which are substantially similar to those described in relation to the solid-state storage device controller 202 of FIG. 2. The write data pipeline 106 includes a packetizer 302 and an error-correcting code (“ECC”) encoder 304. In other embodiments, the write data pipeline 106 includes an input buffer 306, a write synchronization buffer 308, a write program module 310, a compression module 312, an encryption module 314, a garbage collector bypass 316 (with a portion within the read data pipeline 108), a bias module 318, and a write buffer 320. The read data pipeline 108 includes a read synchronization buffer 328, an ECC decoder 322, a depacketizer 324, an alignment module 326, and an output buffer 330. In other embodiments, the read data pipeline 108 may include an inverse bias module 332, a portion of the garbage collector bypass 316, a decryption module 334, a decompression module 336, and a read program module 338.	93	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Data Pipeline	92	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the solid-state storage device controller 202 includes miscellaneous logic 242 that may be customized for a specific application. Typically where the solid-state device controller 202 or master controller 224 is/are configured using a FPGA or other configurable controller, custom logic may be included based on a particular application, customer requirement, storage requirement, etc.	91	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the solid-state storage device controller 202 includes a management controller 234 connected to a management bus 236. Typically the management controller 234 manages environmental metrics and status of the storage device/solid-state storage device 102. The management controller 234 may monitor device temperature, fan speed, power supply settings, etc. over the management bus 236. The management controller 234 may support the reading and programming of erasable programmable read only memory (“EEPROM”) for storage of FPGA code and controller software. Typically the management bus 236 is connected to the various components within the storage device/solid-state storage device 102. The management controller 234 may communicate alerts, interrupts, etc. over the local bus 206 or may include a separate connection to a system bus 240 or other bus. In one embodiment the management bus 236 is an Inter-Integrated Circuit (“I2C”) bus. One of skill in the art will recognize other related functions and uses of a management controller 234 connected to components of the storage device/solid-state storage device 102 by a management bus 236.	90	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the solid-state storage device controller 202 includes a DMA controller 226 that controls DMA operations between the storage device/solid-state storage device 102 and one or more external memory controllers 250 and associated external memory arrays 252 and CPUs 248. Note that the external memory controllers 250 and external memory arrays 252 are called external because they are external to the storage device/solid-state storage device 102. In addition the DMA controller 226 may also control RDMA operations with requesting devices through a NIC 244 and associated RDMA controller 246.	89	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the object index is stored in memory 230, 232 and then periodically off-loaded to a channel of the solid-state storage media 110n or other non-volatile memory. One of skill in the art will recognize other uses and configurations of the memory controller 228, dynamic memory array 230, and static memory array 232.	88	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 9 is a side view of an implementation of an optically transmissive substrate coupled to an implementation of a semiconductor wafer after wafer thinning;	38	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	DESCRIPTION	48	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 18 is a cross sectional view of an implementation of a semiconductor package without through silicon vias (TSVs).	47	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 17 is a side view of an implementation of semiconductor die coupled to an implementation of an optically transmissive substrate after formation of bumps on the first side of the semiconductor die; and	46	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 16 is a side view of an implementation of semiconductor die coupled to an implementation of an optically transmissive substrate after forming a passivation layer;	45	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 15 is a close-up view of an implementation of the first RDL coupled with the second RDL;	44	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 14 is a side view of an implementation of semiconductor die coupled to an implementation of an optically transmissive substrate after formation of a second redistribution layer (RDL);	43	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 13 is a side view of an implementation of semiconductor die coupled to an implementation of an optically transmissive substrate after forming an isolation layer around the plurality of semiconductor die;	42	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 12 is a close-up view of an implementation of an exposed redistribution layer (RDL);	41	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 11 is a side view of an implementation of semiconductor die coupled to an implementation of an optically transmissive substrate after exposing one or more inner terminals of first RDL on the cover glass;	40	Added by DJM 3 2021	3/3/21, 12:00 AM

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