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ONSO3305US - Onsemi346 6.The semiconductor package of claim 1, wherein one or more side walls of the semiconductor die are angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die. 77 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 7.A semiconductor package comprising: 78 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 two or more bumps coupled to a second side of the die on either side of the active area; 81 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 a first redistribution layer (RDL) coupled to each of the two or more bumps and extending to an edge of the semiconductor die; 82 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 an optically transmissive lid coupled to the semiconductor die through the two or more bumps and the first RDL; 83 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die, the second RDL extending to the first side of the semiconductor die. 84 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 8.The semiconductor package of claim 7, wherein the two or bumps are coupled to two or more die pads. 85 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 9.The semiconductor package of claim 7, wherein a pad pitch of the two or more bumps is substantially 60 microns. 86 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 10.The semiconductor package of claim 7, wherein the two or more bumps are copper pillars comprising solder tips. 87 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 11.The semiconductor package of claim 10, wherein a pad pitch of the two or more bumps is substantially 70 microns. 88 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 12.The semiconductor package of claim 5, wherein the two or more bumps comprise solder balls. 89 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 13.The semiconductor package of claim 5, wherein one or more sidewalls of the semiconductor die are angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die. 90 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 14.A method of forming a semiconductor package, the method comprising: 91 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 providing an optically transmissive substrate comprising a first side and a second side; 92 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 forming a first redistribution layer (RDL) on a first side of the optically transmissive substrate, the first RDL comprised over one or more scribe lines comprised on the first side of the optically transmissive substrate; 93 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 providing a semiconductor wafer comprising a first side and a second side, wherein a plurality of active areas is comprised on the second side of the semiconductor wafer and two or more die pads are comprised around each of the plurality of active areas; 94 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 forming two or more inner bumps on each of the two or more die pads 95 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 coupling the second side of the semiconductor wafer to the first side of the optically transmissive substrate, wherein the two or more inner bumps are coupled on either side of the one or more scribe lines; 96 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 thinning the semiconductor wafer to a predetermined thickness; 97 Added by DJM 3 2021 3/3/21, 12:00 AM
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ONSO3305US - Onsemi346 etching the semiconductor wafer to the one or more scribe lines to form a plurality of semiconductor die; 98 Added by DJM 3 2021 3/3/21, 12:00 AM

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