Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	ONSO3305US - Onsemi346	FIG. 10 is a side view of an implementation of an optically transmissive substrate coupled to an implementations of semiconductor die after silicon etching;	39	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended semiconductor packages will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such semiconductor packages, and implementing components and methods, consistent with the intended operation and methods.	49	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 8 is a close-up view of an implementation of an inner bump joint coupled between an implementation of an optically transmissive substrate and an implementation of a semiconductor wafer;	37	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 7 is a side view of an implementation of an optically transmissive substrate coupled to an implementation of a semiconductor wafer;	36	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 6 is a side view of an implementation of a semiconductor wafer after bump formation;	35	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 5 is a side view of an implementation of an optically transmissive substrate after dam formation;	34	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 4 is a top view of an implementation of an optically transmissive substrate having first redistribution layers on the saw streets;	33	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 3 is a side view of an implementation of an optically transmissive substrate;	32	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 2 is a close-up of an implementation of an electrical interconnection route;	31	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	FIG. 1 is a cross sectional view of an implementation of a semiconductor package without through silicon vias (TSVs);	30	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	Implementations will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:	29	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	The method also includes etching of the semiconductor wafer to form a plurality of semiconductor die each coupled to the transmissive substrate. Each semiconductor die includes an active area on the second side of the die. The semiconductor wafer 36 is therefore etched on and around the scribe lines of the semiconductor wafer on the first side of the semiconductor wafer. In various implementations, etching may include wet etching and dry etching and may involve various patterning steps and operations including photolithography. Referring to FIG. 10, the plurality of semiconductor die 52 coupled to the optically transmissive substrate 24 following etching is illustrated. As illustrated, the sidewalls 54 of the semiconductor die 52 are angled. The sidewalls of the semiconductor die are angled during the etching process. In various implementations, the sidewalls may be angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die.	59	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	two or more bumps coupled to two or more die pads on a second side of the die;	69	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	an active area comprised on the second side of the die;	68	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	a semiconductor die comprising a first side and a second side;	67	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	1.A semiconductor package comprising:	66	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	In places where the description above refers to particular implementations of semiconductor packages and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other semiconductor packages.	65	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	The method includes singulating through the passivation layer and the optically transmissive substrate to form a plurality of semiconductor packages. In various implementations, singulating may be performed through, by non-limiting example, sawing, laser cutting, any combination thereof, and other methods for singulating through materials such as glass, metal, plastics, and/or semiconductor materials. Referring to FIG. 18, an implementation of a semiconductor package 68 after singulation is illustrated. As previously described, the semiconductor package 68 includes a first RDL 70 and a second RDL 72 to provide electrical connectivity to the device without the use of TSVs. The first RDL 72 is coupled to the optically transmissive lid 74. In various implementations, the optically transmissive lid may include, by non-limiting example, glass, polycarbonate, acrylic, plastics, or other materials that allow some or all of a desired wavelength of light to pass through the material. The first RDL is also mechanically and electrically coupled with inner bumps 76 which are coupled to the second side of the semiconductor die 78 through die pads 80. In various implementations, two or more die pads are positioned around the active area of the die. The active area 82 of the die 78 may include a sensor area of an image sensor die. The semiconductor die is encapsulated in an isolation layer 84. The semiconductor device including the first RDL 70, second RDL 72, and the isolation layer 84 are encapsulated in a passivation layer 86. In this particular implementation, solder balls are coupled to the second RDL through openings in the passivation layer. In various implementations, other surface mount connection types (pins, studs, stud bumps, pads, etc.) may be used.	64	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	The method also includes forming a passivation layer over each of the plurality of semiconductor die. The passivation layer may protect the semiconductor device from corrosion. In various implementations, the passivation layer may include, by non-limiting example, oxides, nitrides, polyimides and any other material capable of protecting the surface of the semiconductor die. Referring to FIG. 16, the plurality of semiconductor die 52 are illustrated after formation of the passivation layer 64. As illustrated, the passivation layer 64 covers the first side of each of the semiconductor die and also covers the sidewalls of the semiconductor die. The passivation layer couples with the optically transmissive substrate and encapsulates the first RDL and the second RDL. In various implementations, the method includes coupling one or more interconnects with the first side of the semiconductor die. As illustrated in FIG. 17, the interconnects may include a plurality of solder balls 66. The placement and coupling the solder balls 66 may include patterning and etching steps of the passivation layer material to expose the contacts/pads to which the solder balls couple (and some deposition steps if underbump metallizations are employed). In other implementations, the interconnects may include ball grid arrays, copper pillars, or other electrically conductive material for surface mount devices.	63	Added by DJM 3 2021	3/3/21, 12:00 AM
View Edit Delete	ONSO3305US - Onsemi346	The method also includes forming a second redistribution layer (RDL). The second RDL extends from the inner terminals of the first RDL to the first side of each of the plurality of semiconductor die. Referring to FIG. 14, the plurality of die 52 are illustrated after formation of the second RDL 62. In various implementations, the second RDL may be formed of similar material as the first RDL and include a combination of dielectric material and electrically conductive material. By non-limiting example, the RDLs described herein may include, by non-limiting example, polyimide, titanium, copper, nickel, aluminum, alloys thereof, any combination thereof, and other suitable combinations of materials to protect/insulate the semiconductor die and provide conductivity between the die pads of the semiconductor die and the outer electrical terminals of the device. Referring to FIG. 15, an enlargement of area B in FIG. 14 is illustrated. In FIG. 15, the second RDL 62 is illustrated as a single structure (though it is a multi-layered structure) mechanically coupling with the first RDL 32. The second RDL 62 is also electrically coupled with the first RDL 32 and provides connectivity between the first side of the semiconductor die and the second side of the semiconductor die. The second RDL will also provide electrical connectivity to the surface mount interconnect elements and any electrical connection elements within the semiconductor die.	62	Added by DJM 3 2021	3/3/21, 12:00 AM

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