Dave's Patent Content Factory
Applications
Terms
Paragraphs
Claims
Docket
Logout
About
Paragraph #2,521
Edit Paragraph
View
List Paragraphs
Delete
Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
57
Application Number
16455676
Reference Case 1
Reference Case 2
Content
The method also includes coupling the second side of the semiconductor wafer to the first side of the optically transmissive substrate. Referring to FIG. 7, the semiconductor wafer 36 is illustrated coupled to the optically transmissive lid 24. As illustrated, the inner bumps are coupled to the optically transmissive lid 24 on either side of the scribe line. Referring to FIG. 8, an enlargement of area A in FIG. 7 is illustrated. In FIG. 8, the interconnection of the inner bump 46 with the first RDL 32 is illustrated. The inner bump 46 provides the mechanical and electrical coupling between the die pad 44 and the first RDL 32. As illustrated in this particular implementation, the inner bump includes two metal layers. In this implementations, the inner bump includes a copper pillar 48 with a solder tip 50. In various implementations, the die pad pitch may be about 70 microns. In other implementations, the inner bump may include only one metallic material such as a solder. In some implementations, the die pad pitch may be about 60 microns. The size of the pad pitch in semiconductor packages formed using the method described herein is smaller than semiconductor packages using TSVs which can have a pad pitch larger than 200 microns.
Notes
Added by DJM 3 2021
Raw Data
<w:p w14:paraId="6AD7AFE1" w14:textId="7E22988B" w:rsidR="00376FE0" w:rsidRDefault="00FF7013" w:rsidP="003326E6"><w:pPr><w:numPr><w:ilvl w:val="0"/><w:numId w:val="7"/></w:numPr><w:overflowPunct w:val="0"/><w:autoSpaceDE w:val="0"/><w:autoSpaceDN w:val="0"/><w:adjustRightInd w:val="0"/><w:spacing w:line="480" w:lineRule="auto"/><w:rPr><w:szCs w:val="24"/></w:rPr></w:pPr><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">The method also includes coupling the second side of the semiconductor wafer to the first side of the optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> substrate. Referring to FIG. 7, the semiconductor wafer 36 is illustrated coupled to the optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> lid</w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 24</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">. As illustrated, the inner bumps are coupled to the optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> lid </w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">24 </w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>on either side of the scribe line. Referring to FIG. 8, an enlargement of area A in FIG. 7 is illustrated. In FIG. 8, the interconnection of the inner bump 46 with the first RDL 32 is illustrated. The inner bump 46 provides the mechanical and electrical coupling between the die pad 44 and the first RDL 32. As illustrated in this particular implementation, the inner bump includes two metal</w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> layers</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">. </w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>In this implementations, t</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>he inner bump includes a copper pillar 48 with a solder tip 50. In various implementations, the die pad pitch may be</w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> about</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 70 microns. In other implementations, the inner bump may include only one </w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">metallic </w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>material such as</w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> a</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> solder. In </w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:lastRenderedPageBreak/><w:t xml:space="preserve">some implementations, the die pad pitch may be </w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">about </w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">60 microns. The size of the pad pitch in semiconductor packages formed using the method described herein is smaller than semiconductor packages using TSVs which can </w:t></w:r><w:r w:rsidR="0071784B"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>have a pad pitch</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> larger than 200 microns. </w:t></w:r></w:p>
Submit