Dave's PCF WIP: Paragraphs

Paragraphs

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View Edit Delete	FSP1845	Additionally, die group configurations where none of the dies include an ODT resistance circuit may be less than optimal since none of the dies of the die group can terminate the transmission line with a termination resistance at a low level. In turn, the transmission line 308 is limited in terms of the frequency, bandwidth, and/or data rate of the signals that it can transmit with sufficient quality. Accordingly, configuring at least one of the dies of the die group 306, such as the end die 310, with an ODT resistance circuit, while configuring at least one of the other dies without an ODT resistance circuit, may provide an optimal combination of dies with and without ODT resistance circuits that desirably terminates the transmission line 308 with a low resistance level at the memory side while reducing the effective die capacitance, which in turn allows for signals to be communicated over the transmission line 308 between the controller die 102 and the die group 306 at higher frequencies, bandwidth, and/or data rates.	105	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, by reducing the number of dies of the die group 306 that includes an ODT resistance circuit, power consumption may be reduced. The number of commands communicated over the transmission lines 134 to set the ODT resistances to the die group 306 may also be reduced, simplifying the overall process to set ODT resistance for communication between the controller die 102 and the die group 306.	106	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In various example methods of operation, when the controller die 102 and the memory dies 304 communicate with each other over the transmission line 308--either by the controller die 102 transmitting a signal over the transmission line 308 to the memory dies 304, or one of the memory dies 304 transmitting a signal over the transmission line 308 to the controller die 102--the ODT resistance circuit 328 is set to the low resistance level. In some embodiments, the controller die 102 and the memory die 304 may be configured to communicate with each other over the transmission line 308 at different frequencies, including a high frequency and a low frequency. The high frequency and the low frequency may be predetermined values, where, in general, the high frequency is a higher value than the low frequency. During communication over the transmission line 308, whether the ODT resistance circuit 328 is set to the high level or the low level may depend on whether signal communicated over the transmission line is communicated at the high frequency or the low frequency. For such embodiments, when the controller die 102 and the memory dies 304 communicate at the high frequency, the end die 310 has the ODT resistance circuit 328 set to the low resistance level. Alternatively, when the controller die 102 and the memory dies 304 communicate at the low frequency, the end die 310 has the ODT resistance circuit 328 set to the high resistance level.	107	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some example embodiments, the end die 310 is a "dummy" die for the die group 306, in that it only has I/O contact pads and ODT resistance circuits coupled to the transmission lines 134, and/or its sole function is to provide memory-side termination resistances for the transmission lines 134. For other example embodiments, such as the one shown in FIG. 3, the end die 310 includes additional circuitry 330--i.e., in addition to I/O contact pads and ODT resistance circuits. The additional circuitry 330 may be configured to perform one or more functions for the memory system 100 other than provide a memory-side termination resistance for the transmission lines 134. For example, in some example embodiments, the end die 310 is another one of the memory dies 104, configured to store data, like the memory dies 304. Accordingly, the additional circuitry 330 includes at least some of the components of the memory die 104 shown in FIG. 2B. In other example embodiments, the additional circuitry 330 includes error correction circuitry that is configured to detect and/or correct for errors in signals communicated over the transmission lines 134, and/or perform diagnostics such as parity checks or bit error rate estimation. Other types of additional circuitry 330, and/or functions other than those for storing data, performing error correction or detection, or other diagnostics, may be possible.	108	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, in various example embodiments, the end die 310 may be the same size as the memory dies 304, or may have a smaller size than the memory dies 304. In particular embodiments, the end die 310 may be a smaller die where the end die is not also a memory die, and in turn does not require as large of a size as the memory dies 304. A smaller die may desirably reduce the size and/or cost associated with the die group 306.	109	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 3 shows a physical layout of an example configuration of at least some of the components of the controller die 102 and the plurality of memory dies 104 shown in FIGS. 1A-2B. In FIG. 3, at least some of the memory dies 104 are represented by an N-number memory dies 304, including a first memory die 304(1), a second memory die 304(2), and an Nth memory die 304(N). In various embodiments, N may be any integer of two or more. The N-number of memory dies 304(1)-304(N) may be all of the memory dies 104 in the memory system 100, or may be less than all of the memory dies 104. For example, the N-number of memory dies 304(1)-304(N) may be located on the same chip and/or may be part of the same chip enable group. The memory system 100 may include a single chip or chip enable group in which the memory dies 104 are located. The N-number of memory dies 304 of FIG. 3 may be representative of that single chip or chip enable group of dies. Alternatively, the memory system 100 may include multiple chips or chip enable groups, and some of the memory dies 104 may be located on one chip or in one chip enable group, while other memory dies 104 may be located on one or more other chips or in one or more other chip enable groups. The N-number of memory dies 304 of FIG. 3 may be representative of one of the plurality of chips or chip enable groups. In addition or alternatively, the N-number of memory dies 304 may be configured as or part of the same die stack. Various configurations are possible. Further details of dies configured as a die stack are described in further detail below with reference to FIG. 4.	71	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory die 104 may further include a page buffer or data cache 144 that caches data that is sensed from and/or that is to be programmed to the memory cell structure 142. The memory die 104 may also include a row address decoder 146 and a column address decoder 148. The row address decoder 146 may decode a row address and select a particular wordline in the memory array 142 when reading or writing data to/from the memory cells in the memory array 142. The column address decoder 148 may decode a column address to select a particular group of bitlines in the memory array 142 to be electrically coupled to the data cache 144.	65	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.	61	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.	60	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.	59	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.	58	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.	57	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).	62	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the memory-side interface 156 may include input/output (I/O) contact pad portions 160 in communication with the memory I/O circuitry 158. For example, the signals that the memory I/O circuitry 158 generates for transmission to the controller die 102 may be communicated from the output driver circuits of the memory I/O circuitry 158 to the I/O contact pads 160. Similarly, the signals that the memory-side interface 156 receives from the controller die 102 may be sent from the I/O contact pads 160 to input circuits (e.g., input buffer circuits) of the memory I/O circuitry 158. In addition, as described in further detail below, the I/O contact pads 160, along with wire bond elements (WBE) (shown in FIG. 3) may form or be part of the transmission lines 134 over which the memory dies 104 and the controller die 102 communicate signals between each other.	69	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, in at least some embodiments, as shown in FIG. 2B, the memory-side interface 156 may include on-die termination (ODT) resistance circuitry 162, which may include one or more resistors or other circuit components (active and/or passive) providing a resistance. The on-die termination resistance circuitry 162 may provide termination resistance or impedance for the transmission lines 134, and may be used for impedance matching between the memory dies 104 and the transmission lines 134. The on-die termination resistance circuitry 162 may be connected to the I/O contact pads 160. In addition, for at least some embodiments, the on-die termination resistance circuitry 162 may provide variable resistance levels or values, including one or more high levels and one or more low levels, as described in further detail below. The resistance levels or values that the on-die termination resistances provide may be controlled by the controller die 102, the on-die control logic 152, or a combination thereof.	70	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory-side interface 156 may include memory input/output (I/O) circuitry 158 that is configured to send, receive, and generate signals, including data signals carrying data, command signals identifying commands, clock signals, or other types of signals carrying other information to be transmitted to and received from the controller die 102. For example, data sensed into the data cache 144 may be sent to the memory I/O circuitry 158 for transmission to the controller die 102. Similarly, data received from the controller die 102 may be received by the memory I/O circuitry 158, and the memory I/O circuitry 158 may communicate the data to the data cache 144. Additionally, commands to be communicated between the controller die 102 and the control logic 152 may be communicated via the memory I/O circuitry 158. The memory I/O circuitry 158 may be configured similar to and/or have similar or the same circuit topologies have any of various circuit or combinations of circuits, including output driver circuits, such as in the form of push-pull circuits, to generate and output signals onto the transmission lines 134, and input buffers, such as in the form of comparators and/or Schmitt trigger circuits to receive signals on the transmission lines 134. Any of various suitable circuit configurations to transmit, receive, and generate signals and connect to the transmission lines 134 to communicate the signals may be possible.	68	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the memory dies 304 may be part of a group of dies (or die group) 306 that further includes an end (or termination) die 310. The end die 310 is described in further detail below.	72	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In the example configuration shown in FIG. 3, the group of dies 306, including the memory dies 304 and the end die 310, may be configured in and/or integrated with a packaging that includes various packaging components, including a package or die substrate 302 on which the die group 306 is disposed or mounted, and an outer encasing or cover 312 that encases, covers, houses, and/or protects the dies of the die group 306. Other packaging components may be included, such as traces and vias integrated in the die substrate 302, solder balls, contact pads, and/or wire bonds, as non-limiting examples, at least some of which are described in further detail below. The controller die 102 may be configured and/or implemented as its own chip and/or integrated with its own packaging separate to that of the die group 306. (For simplicity, packaging components of the controller die 102 are not shown in FIG. 3). The controller die 102 and the die group 306 integrated with the packaging may be integrated, mounted, or disposed on a printed circuit board 314, as shown in FIG. 3.	73	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller die 102 and the memory dies 304(1)-304(N) may communicate signals between each other on transmission lines (e.g., at least some of the transmission lines 134 of FIGS. 2A and 2B) connecting the controller die 102 and the memory dies 304(1)-304(N). For simplicity, the physical layout of FIG. 3 shows a single transmission line 308 connecting the controller die 102 and the memory dies 304. However, in actual implementation as described with reference to FIGS. 2A and 2B, there may be multiple transmission lines between the controller 102 and the memory dies 304(1)-304(N) configured to communicate data signals, clock signals, strobe signals, command signals, status signals, or any other type of signals between the controller die 102 and the memory dies 304. The multiple (at least two) transmission lines may be configured in parallel with each other such that two or more signals propagating on two or more parallel transmission lines may be communicated separately and/or simultaneously.	74	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the transmission line 308 may be a unidirectional transmission line or a bidirectional transmission line. A unidirectional line is a transmission line that is configured to communicate signals one way or in one direction, either only from the controller die 102 to the memory dies 304, or only from the memory dies 304 to the controller die 102. In contrast, a bidirectional line is a transmission line that is configured to communicate signals both ways or in both directions, from the controller die 102 to the memory dies 304, and from the memory dies 304 to the controller die 102. For configurations that include multiple transmission lines, in various embodiments, all of the transmission lines may be unidirectional lines, all of the transmission lines may bidirectional lines, or the transmission lines may include a combination of at least one unidirectional line and at least one bidirectional line. Various configurations of unidirectional and/or bidirectional transmission lines may be possible.	75	Added by DJM 12 2021	12/22/21, 12:00 AM

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