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The memory-side interface 156 may include memory input/output (I/O) circuitry 158 that is configured to send, receive, and generate signals, including data signals carrying data, command signals identifying commands, clock signals, or other types of signals carrying other information to be transmitted to and received from the controller die 102. For example, data sensed into the data cache 144 may be sent to the memory I/O circuitry 158 for transmission to the controller die 102. Similarly, data received from the controller die 102 may be received by the memory I/O circuitry 158, and the memory I/O circuitry 158 may communicate the data to the data cache 144. Additionally, commands to be communicated between the controller die 102 and the control logic 152 may be communicated via the memory I/O circuitry 158. The memory I/O circuitry 158 may be configured similar to and/or have similar or the same circuit topologies have any of various circuit or combinations of circuits, including output driver circuits, such as in the form of push-pull circuits, to generate and output signals onto the transmission lines 134, and input buffers, such as in the form of comparators and/or Schmitt trigger circuits to receive signals on the transmission lines 134. Any of various suitable circuit configurations to transmit, receive, and generate signals and connect to the transmission lines 134 to communicate the signals may be possible.

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<w:p w14:paraId="033CC029" w14:textId="77777777" w:rsidR="00EE2B08" w:rsidRDefault="00EE2B08"><w:r><w:t xml:space="preserve">The memory-side interface 156 may include memory input/output (I/O) circuitry 158 that is configured to send, receive, and generate signals, including data signals carrying data, command signals identifying commands, clock signals, or other types of signals carrying other information to be transmitted to and received from the controller die 102. For example, data sensed into the data cache 144 may be sent to the memory I/O circuitry 158 for transmission to the controller die 102. Similarly, data received from the controller die 102 may be received by the memory I/O circuitry 158, and the memory I/O circuitry 158 may communicate the data to the data cache 144. Additionally, commands to be communicated between the controller die 102 and the control logic 152 may be communicated via the memory I/O circuitry 158. The memory I/O circuitry 158 may be configured similar to and/or have similar or the same circuit topologies have any of various circuit or combinations of circuits, including output driver circuits, such as in the form of push-pull circuits, to generate and output signals onto the transmission lines 134, and input buffers, such as in the form of comparators and/or Schmitt </w:t></w:r><w:r><w:lastRenderedPageBreak/><w:t xml:space="preserve">trigger circuits to receive signals on the transmission lines 134. Any of various suitable circuit configurations to transmit, receive, and generate signals and connect to the transmission lines 134 to communicate the signals may be possible. </w:t></w:r></w:p>