Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	FSP1845	In other embodiment, an apparatus includes: a controller die, and a group of dies configured to communicate with the controller die via a transmission line, wherein the group of dies comprises a plurality of memory dies and an end die. The group of dies includes at least one on-die termination circuit coupled to the transmission line. Additionally, less than all of the group of dies comprises a respective one of the at least one on-die termination circuit.	21	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the group of dies is configured to communicate over the transmission line at a predetermined high frequency and at a predetermined low frequency, and wherein the on-die termination resistance circuit is configured to: set an associated resistance at a low level when the group of dies communicates over the transmission line at the predetermined high frequency; and set the associated resistance at a high level when the group of dies communicates over the transmission line at the predetermined low frequency.	20	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the die stack comprises a staircase stack.	19	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the group of dies is configured as a die stack.	18	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the group of dies is coupled to the transmission line via a wire bond portion of the transmission line.	17	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the first die comprises an end die of the group.	16	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, wherein none of the other dies of the group, except the first die, comprises a respective on-die termination resistance circuit coupled to the transmission line.	15	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the controller die and the group of dies are configured to communicate over the transmission line at a predetermined high frequency and at a predetermined low frequency. The at least one on-die termination resistance circuit is configured to: set an associated resistance at a low level for communication over the transmission line at the predetermined high frequency, and set the associated resistance at a high level for communication over the transmission line at the predetermined low frequency.	30	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Overview	13	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 6 is an alternative configuration for the group of dies of FIG. 3, where at least one of the N-number of memory dies also include an on-die termination resistance circuit.	12	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 5 is a circuit model of a wire bond portion of the transmission line of FIG. 3.	11	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 4 is a side view of a plurality of dies integrated as a staircase stack.	10	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 3 is a physical layout of an example configuration of at least some of the components of the controller and a group of dies including an N-number of memory dies and an end die coupled to a transmission line.	9	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 2B is a block diagram of example components of a non-volatile memory die of the memory system of FIG. 1A.	8	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 2A is a block diagram of example components of a controller of the memory system of FIG. 1A.	7	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1C is a block diagram of a hierarchical storage system.	6	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1B is a block diagram of a storage module that includes a plurality of memory systems.	5	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1A is a block diagram of an example memory system.	4	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The accompanying drawings, which are incorporated in and constitute a part of this specification illustrate various aspects of the invention and together with the description, serve to explain its principles. Wherever convenient, the same reference numbers will be used throughout the drawings to refer to the same or like elements.	3	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller die 102 may include a buffer manager/bus controller module 114 that manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration for communication on an internal communications bus 117 of the controller die 102. A read only memory (ROM) 118 may store and/or access system boot code. Although illustrated in FIG. 2A as located separately from the controller die 102, in other embodiments one or both of the RAM 116 and the ROM 118 may be located within the controller die 102. In yet other embodiments, portions of RAM 116 and ROM 118 may be located both within the controller die 102 and outside the controller die 102. Further, in some implementations, the controller die 102, the RAM 116, and the ROM 118 may be located on separate semiconductor dies.	44	Added by DJM 12 2021	12/22/21, 12:00 AM

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