Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
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View Edit Delete	FSP1845	Additionally, the ODT resistance circuit 328 may be configured to change or adjust its resistance from a first resistance level to a second resistance level. The first and second resistance levels may be any of various combinations of high and low resistance levels. That is, depending on the configuration, the ODT resistance circuit 328 may be configured to change its resistance from a high resistance level to a low resistance level, from a low resistance level to a high resistance level, from a first high resistance level of a plurality of high resistance levels to a second high resistance level of the plurality of high resistance levels (where the first high resistance level can be either higher or lower than the second high resistance level), or from a first low resistance level of a plurality of low resistance levels to a second low resistance level of the plurality of low resistance levels (where the first low resistance level can be either higher or lower than the second low resistance level).	95	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The resistance levels that the ODT resistance circuit 328 may be set to may include at least two levels, including a high resistance level and a low resistance level. In addition, for at least some example configurations, the resistance levels may include a plurality of low levels, and/or a plurality of high levels. Accordingly, at a given moment in time, the ODT resistance circuit 328 may be configured to set its resistance to one of a plurality of high resistance levels and/or to set its resistance value to one of a plurality of low resistance levels.	94	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Any suitable type of memory can be used for the memory cells 142. As examples, the memory can be dynamic random access memory ("DRAM") or static random access memory ("SRAM"), non-volatile memory, such as resistive random access memory ("ReRAM"), electrically erasable programmable read only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), magnetoresistive random access memory ("MRAM"), phase-change memory ("PCM"), or other elements comprising semiconductor or other material capable of storing information. Each type of memory may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.	56	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The portion of the transmission line 308 that extends over the wire bond portion 320 may have an associated characteristic impedance dependent on inductance values of the wire bonds 320 and the die capacitance of the dies 304, 310 of the die group 306. FIG. 5 shows a circuit schematic diagram of the inductance L provided by the wire bonds 320 and the die capacitance C(M) of the dies 304 corresponding to the configuration of FIG. 3. In particular, a first inductor L.sub.320(1) indicates the inductance of the first wire bond 320(1), a second inductance L.sub.320(2) indicates the inductance of the second wire bond 320(2), a third inductance L.sub.320(3) indicates the inductance of the third wire bond 320(3), and an (N+1)th inductance L.sub.320(N+1) indicates the inductance of the (N+1)th wire bond 320(N+1). Additionally, a first capacitor C(M1) represents a die capacitance of the first memory die 304(1), a second capacitor C(M2) represents a die capacitance of the second memory die 304(2), and an (N+1)th capacitor C(M(N+1)) represents a die capacitance of the end die 310. As shown in FIG. 5, the inductors L.sub.320 are connected in series with each other, and the die capacitances C(M) are connected in shunt with respect to the inductors L.sub.320 and with reference to ground (GND). The associated characteristic impedance of the wire bonds 320 is dependent on or determined by the square root of the inductance L divided by the capacitance C.	92	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Similarly, FIG. 3 shows each of the memory dies 304 as including respective memory I/O circuitry 158, as previously described with respect to FIG. 2B. For example, in FIG. 3, the first memory die 304(1) includes first memory I/O circuitry 158(1), the second memory die 304(2) includes second memory I/O circuitry 158(2), and the Nth memory die 304(N) includes Nth memory I/O circuitry 158(N). Each of the memory I/O circuitries 158 is configured to send and/or receive signals communicated on the transmission line 308. For situations or embodiments where a given kth memory die 304(k) is to send a signal (e.g., a data signal, a clock signal, or a command signal) to the controller die 102 via the transmission line 308, an output driver circuit of the kth memory I/O circuitry 158(k) generates and outputs the signal to the transmission line 308. In addition, for situations or embodiments where a given kth memory die 304(k) is to receive a signal from the controller die 102 via the transmission line 308, an input circuit (e.g., an input buffer circuit) of the kth memory I/O circuitry 158(k) is configured to receive the signal from the transmission line 308.	91	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Referring back to FIG. 3, the controller die 102 is shown as including the controller I/O circuitry 136, which is configured to send and receive signals communicated on the transmission lines 134, as previously described with respect to FIG. 2A. With respect to the configuration in FIG. 3, the controller I/O circuitry 136 is configured to send and receive signals communicated on the transmission line 308. For situations or embodiments where the controller 102 is to send a signal (e.g., a data signal, a clock signal, or a command signal) to the memory dies 304 via the transmission line 308, an output driver circuit of the controller I/O circuitry 136 generates and outputs the signal to the transmission line 308. In addition, for situations or embodiments where the controller 102 is to receive a signal from the memory dies 304 via the transmission line 308, an input circuit (e.g., an input buffer circuit) of the controller I/O circuitry 136 is configured to receive the signal from the transmission line 308.	90	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The staircase stack of dies 402 may also be configured with an N-number of wire bond elements 408. In particular, a first wire bond element 408(1) connects to the first I/O contact pad 406(1) of the first die 402(1) and to a contact pad 410 of the die substrate 404. In addition, the second through (N+1)th wire bonds 408(2) to 408(N+1) are each connected to two I/O contact pads 406 of two adjacent dies 402 in the staircase stack. For example, a second wire bond 408(2) is connected to the first I/O contact pad 406(1) on the first die 402(1) and the second I/O contact pad 406(2) of the second die 402(2); a third wire bond 408(3) connects to the second I/O contact pad 406(2) of the second die 402(2) and to the third I/O contact pad 406(3) of the third die 402(3); an Nth wire bond element 408(N) connects to an (N-1)th I/O contact pad 406(N-1) of an (N-1)th die 402(N-1) (not shown) and to the Nth I/O contact pad 406(N) of the Nth die 402(N); and (N+1)th wire bond element 408(N+1) connects to the Nth I/O contact pad 406(N) of an Nth die 402(N) and to the (N+1)th I/O contact pad 406(N+1) of the (N+1)th die 402(N+1).	89	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, each of the dies 402 may have respective I/O contact pads 406. The side view of FIG. 4 shows an I/O contact pad 406 on each of the dies 402, with the first memory die 402(1) including a first contact pad 406(1), the second memory die 402(2) including a second contact pad 406(2), the third memory die 402(3) including a third contact pad 406(3), the Nth memory die 402(N) including an Nth contact pad 406(N).	88	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In the example configuration shown in FIG. 4, the stack of dies 402 may be disposed on a die substrate 404. In particular, a first memory die 402(1) may be in contact with and/or be the closest of the memory dies 402 to the die substrate 404. The other memory dies 402(2)-402(N+1) are stacked on the first memory die 402(1) in a staircase configuration such that the second memory die 402(2) is disposed on the first memory die 402(1), the third memory die 402(3) is disposed on the second memory die 402(2), and the (N+1)th (or end) die 402(N+1) is disposed on an Nth memory die 402(N).	87	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 4 shows a side view of a plurality of dies 402 integrated or configured as a staircase stack. The plurality of dies 402 includes an N-number of memory dies 402(1) to 402(N) that are representative of the N-number memory dies 304(1)-304(N), and an (N+1)th die 402(N+1) that is representative of the end die 310 of the die group 306. The plurality of dies 402 illustrate an example configuration in which the die group 306 may be integrated with each other and the packaging.	86	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	One type of die stack is a staircase stack. In a staircase stack, the dies may be stacked on top of one another such that the dies do not completely cover each other. Instead, each die has an exposed portion where respective I/O contact pads may be disposed and connected with each other via wire bonds. By disposing the dies on top of one another to create exposed portions, the dies of the die stack, when viewed from the side, have a "staircase" shape, which each die being one of the "steps" of the staircase.	85	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The die group 306 may be configured in any of various ways within the memory system 100. In one example configuration, the die group 306 is configured as a die stack. In general, a given die may be a generally planar structure having two opposing planar surfaces, including a first planar surface and a second planar surface. In a die stack, the dies may be disposed on or "stacked" on top of one another, starting with a first or base die and extending in a direction perpendicular to planar surfaces of the dies. As a die stack, one planar surface of one die may face and/or contact a planar surface of a second die. Also, two dies are adjacent to each other where no other dies of the stack are disposed in between them. Also, in some example configurations, a first or base die may be disposed or mounted on a base substrate or a printed circuit board directly. A last die of the stack may be the die that is disposed furthest from the base substrate or printed circuit board on which the die stack is mounted.	84	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory dies 304, the wire bond elements 320, and the I/O contact pad 322 are numbered in FIG. 3 to correspond to their respective positions in the transmission line 308. Given an index k, the higher the value of k, the further away a kth memory die 304(k), a kth wire bond element 314(k), and/or a kth I/O contact pad 316(k) are electrically along the transmission line 308 from the packaging portion 318, the PCB portion 316, and the controller die 102. In this context, the (N+1)th I/O contact pad 322(N+1) is the electrically furthest of the I/O contact pads 322 along the transmission line 308 from the packaging portion 318, the PCB portion 316, and/or the controller die 102, and, in turn, is or functions as a memory-side end or termination of the transmission line 308. In this context, the end die 310 is the die that is the furthest of the dies of the die group 306 from the packaging portion 318, the PCB portion 316, and/or the controller die 102 with reference to the transmission line 308. In addition or alternatively, the end die 310 is the die that includes the (N+1)th I/O contact pad 322(N+1) that functions as the memory-side end or termination of the transmission line 308.	83	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The wire bonds 320 and the I/O contact pads 322, in combination, may form a part or a portion of the transmission line 308, with each wire bond 320 and each I/O contact pad 322 having positions relative to each other in the transmission line 308 that correspond to propagation delay or electrical distance from the packaging portion 318. A signal transmitted from the controller die 102 on the transmission line 308 may take a shorter amount of time to reach a given I/O contact pad 322 or a given wire bond element 320 that is positioned electrically closer to the packaging portion 318, compared to a given I/O contact pad or a given wire bond element positioned electrically farther from the packaging portion 318, along the transmission line 308.	82	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	By way of introduction, the below embodiments relate to reducing effective die capacitance through elimination of on-die termination (ODT) resistance circuits from one or more dies of a die group, such as a die stack, which in turn, may allow for increased frequency, bandwidth, and/or data rates over transmission lines coupled to the die group. In one embodiment, an apparatus that includes a transmission line and a group of dies coupled to the transmission line. The group of dies includes: a first die configured with an on-die termination resistance circuit coupled to the transmission line; and a second die configured without any on-die termination resistance circuits coupled to the transmission line.	14	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the end die does not include additional circuitry other than input/output contact pads and on-die resistance circuits.	26	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the end die is configured to perform error correction.	25	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the end die is configured to store data.	24	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the only one of the dies comprises the end die.	23	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, only one of the dies of the group comprises the at least one on-die termination circuit coupled to the transmission line.	22	Added by DJM 12 2021	12/22/21, 12:00 AM

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