16/146,238

Paragraph Number

71

FIG. 3 shows a physical layout of an example configuration of at least some of the components of the controller die 102 and the plurality of memory dies 104 shown in FIGS. 1A-2B. In FIG. 3, at least some of the memory dies 104 are represented by an N-number memory dies 304, including a first memory die 304(1), a second memory die 304(2), and an Nth memory die 304(N). In various embodiments, N may be any integer of two or more. The N-number of memory dies 304(1)-304(N) may be all of the memory dies 104 in the memory system 100, or may be less than all of the memory dies 104. For example, the N-number of memory dies 304(1)-304(N) may be located on the same chip and/or may be part of the same chip enable group. The memory system 100 may include a single chip or chip enable group in which the memory dies 104 are located. The N-number of memory dies 304 of FIG. 3 may be representative of that single chip or chip enable group of dies. Alternatively, the memory system 100 may include multiple chips or chip enable groups, and some of the memory dies 104 may be located on one chip or in one chip enable group, while other memory dies 104 may be located on one or more other chips or in one or more other chip enable groups. The N-number of memory dies 304 of FIG. 3 may be representative of one of the plurality of chips or chip enable groups. In addition or alternatively, the N-number of memory dies 304 may be configured as or part of the same die stack. Various configurations are possible. Further details of dies configured as a die stack are described in further detail below with reference to FIG. 4.

Added by DJM 12 2021