Paragraph 61

Paragraph 61

Application: FSP1845

Matter Number FSP1845
Paragraph Number 61
Application Number 16/146,238
Reference Case 1 FSP1845
Reference Case 2
Created 12/22/21, 12:00 AM
Modified 12/22/21, 12:00 AM
Id 6,574
Content
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
Notes Added by DJM 12 2021