Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	FSP1845	FIG. 2B is a block diagram illustrating exemplary components of one of the memory dies 104 in more detail. The non-volatile memory die 104 may include a memory cell structure 142. In some example configurations, the memory cell structure 142 may be configured in the form of an array, such as two-dimensional or a three-dimensional array.	55	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additional modules of the non-volatile memory system 100 illustrated in FIG. 2A may include a media management layer 138, which may perform certain memory functions, such as address management (e.g., address translation) and wear leveling of memory cells of the memory dies 104. The memory system 100 may also include other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with the controller die 102. In alternative embodiments, one or more of the RAID module 128, media management layer 138 and buffer management/bus controller 114 are optional components that may not be necessary in the controller die 102.	54	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the memory interface 130 and/or the controller I/O circuitry 136 may be configured to communicate with the memory dies 104 over the transmission lines 134 using any of various transmission modes, types, protocols, standards, or formats, non-limiting examples of which include double data rate (DDR), and/or a Toggle Mode (TM), such as TM 200, 400, or 800.	53	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the memory interface 130 may include or be in communication with controller input/output (I/O) circuitry 136, which includes the circuitry that sends, receives, and generates the analog signals communicated on the transmission lines 134. The controller I/O circuitry 136 may include any of various configurations or circuitry topologies to send, receive, and generate signals. For example, to generate and output signals onto the transmission lines 134, the controller I/O circuitry 136 may include output driver circuits, such as in the form of push-pull circuits, that generate analog signals on the transmission lines 134 at certain predetermined high and low voltage levels. Also, to receive signals from the transmission lines 134, the controller I/O circuitry 136 may include input circuitry, such as in the form of input buffers, which, in some embodiments, may include comparators, such as Schmitt triggers or differential comparators, as non-limiting examples. In various embodiments, the I/O circuitry 136 may include other circuit components, such as pre-driver circuits, level shifter circuits, sampling circuits (e.g., latches or flip flops), and/or multiplexers, to transmit, receive, and generate the signals communicated on the transmission lines. Additionally, the controller I/O circuitry 136 may include conductive components, such as I/O contact pads disposed on the controller die 102 that connect to the transmission lines 134.	52	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller 102 may be coupled to the transmission lines 134 via its memory interface 130. When the controller die 102 wants to send a signal to the memory dies 104, the controller die 102 may send the signal through its memory interface 130 onto one of the transmission lines 134. The memory dies 104 may each have their own respective memory interfaces to send and receive signals, as described in further detail below with respect to FIG. 3. When referring to the memory interfaces, the memory interface of the controller die 102 may be referred to as a controller-side memory interface 130, and the memory interfaces of the memory dies 104 may be referred to as memory-side memory interfaces.	51	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	As shown in FIG. 2A, the memory system 100 may include a plurality of transmission (Tx) lines (or channels) 134 connecting the controller die 102 and the plurality of memory dies 104. In general, a transmission line is any conductive structure or combination of conductive structures configured to conduct alternating current (AC) or radio frequency (RF) signals from a transmitter that is transmitting the signals to a receiver that is receiving the signals. For the example memory systems described herein, transmission lines are included to communicate signals between (including to and from) the controller die 102 and the memory dies 104. The controller die 102 and the memory dies 104 may be configured to communicate signals--including data signals, clock signals, and command signals--over the plurality of transmission (Tx) lines 134. A signal that is communicated between the controller die 102 and the memory dies 104 may be either transmitted from the controller die 102 over one of the transmission lines 134 to the memory dies 104, or transmitted from the memory dies 104 over one of the transmission lines 134 to the controller die 102. In this context, the controller die 102 and each of the memory dies 104 may be configured as transceiver circuits (or dies) in that they may each be configured to transmit and receive signals.	50	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory interface 130 is configured to output the command sequences or context commands to the memory dies 104 and receives status information from the memory dies 104. Along with the command sequences and status information, the memory interface 130 may also be configured to send and receive data, such as in the form of data signals, to be programmed into and read from the memory dies 104. The memory interface 130 may also be configured to output clock signals or strobe signals to control the timing at which the memory dies 104 receive data signals carrying data to be programmed and/or at which the memory dies 104 output data signals carrying data the controller die 102 wants read from the memory dies 104.	49	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The command sequencer 128 may be configured to generate command sequences, such as program, read, and erase command sequences, to be transmitted to the memory dies 104. The commands of the command sequences that the command sequencer 128 outputs may be referred to as context commands. For example, commands of command sequences for read operations may be referred to as read context commands, and commands of command sequences for write operations may be referred to as write context commands.	48	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the back end module 110 may include a command sequencer 128 and a memory interface 130. The controller die 102 may include a control layer 132 (e.g., a flash controller layer) that controls the overall operation of the back end module 110.	47	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The back end module 110 may include an error correction controller (ECC) engine 124 that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the memory dies 104. Additionally, the back end module 110 may include a RAID (Redundant Array of Independent Drives) module 128 that manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the memory system 100. In some cases, the RAID module 128 may be a part of the ECC engine 124.	46	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the front end module 108 may include a host interface 120 and a physical layer interface (PHY) 122 that provide the electrical interface with the host or next level storage controller. The choice of the type of the host interface 120 can depend on the type of memory being used. Examples types of the host interface 120 may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 120 may typically facilitate transfer for data, control signals, and timing signals.	45	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	A memory system may communicate signals carrying data, command, or clocking information for the storage of data within the memory system. The signals may be communicated along signal paths or transmission lines. The memory system may include memory dies that include the storage elements that store data. The memory dies have an associated die capacitance, which in turn affects the characteristic impedances of the transmission lines and the operation frequency or bandwidth at which signals over the transmission lines may be communicated. In general, higher die capacitance limits the frequency or bandwidth at which the signals can be communicated. Accordingly, ways to improve die capacitance to allow for increased frequency and bandwidth without degrading signal quality may be desirable.	2	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 2A is a block diagram illustrating exemplary components of the controller die 102 in more detail. The controller die 102 may include a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the memory dies 104, and various other modules that perform various functions of the memory system 100. In general, a module may be hardware or a combination of hardware and software. For example, each module may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. In addition or alternatively, each module may include memory hardware that comprises instructions executable with a processor or processor circuitry to implement one or more of the features of the module. When any one of the module includes the portion of the memory that comprises instructions executable with the processor, the module may or may not include the processor. In some examples, each module may just be the portion of the memory that comprises instructions executable with the processor to implement the features of the corresponding module without the module including any other hardware. Because each module includes at least some hardware even when the included hardware comprises software, each module may be interchangeably referred to as a hardware module.	43	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1B illustrates a storage module 200 that includes a plurality of memory systems 100. As such, the storage module 200 may include a storage controller 202 that interfaces with a host and with a storage system 204, which includes a plurality of memory systems 100. The interface between the storage controller 202 and memory systems 100 may be a bus interface, such as a serial advanced technology attachment (SATA), a serial attached SCSI (SAS), a peripheral component interface express (PCIe) interface, an embedded MultiMediaCard (eMMC) interface, a SD interface, or a Universal Serial Bus (USB) interface, as non-limiting examples. The storage system 200, in one embodiment, may be a solid state drive (SSD), such as found in portable computing devices, such as laptop computers and tablet computers, and mobile phones.	41	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The interface between the controller die 102 and the memory dies 104 may be any suitable memory interface, such as Toggle Mode 200, 400, or 800. In one embodiment, the memory system 100 may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, the system 100 may be part of an embedded memory system.	40	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller die 102 is configured to manage data stored in memory cells of the memory dies 104 and also to communicate with a host, such as a computer or electronic device. The controller die 102 can have various functionality in addition to the specific functionality described herein. For example, the controller die 102 can format the memory cells and/or the circuitry of the memory dies 104 to ensure the memory dies 104 operate properly, map out bad or defective memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the controller die 102 and implement other features. In operation, when a host needs to read data from or write data to the memory die 104, the host communicates with the controller die 102. If the host provides a logical address to which data is to be read/written, the controller die 102 can convert the logical address received from the host to a physical address in the memory dies 102. (Alternatively, the host can provide the physical address). The controller die 102 may also be configured to perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused).	39	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller die 102 can take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example. The controller die 102 can be configured with hardware and/or firmware to perform the various functions described below. Also, some of the components shown as being internal to the controller die 102 can also be stored external to the controller die 102, and other components can be used. Additionally, the phrase "operatively in communication with" could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein.	38	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1A is a block diagram illustrating a memory system 100, such as a non-volatile memory system. The memory system 100 may include a controller 102 and memory that may be made up of a plurality of memory dies 104. As used herein, the term memory die refers to the set of memory cells (including non-volatile memory cells), and associated circuitry for managing the physical operation of those memory cells, that are formed on a single semiconductor substrate. In addition, the term die, in general, may refer to circuitry or circuit components on a single semiconductor substrate, but may or may not include memory cells to store data. The controller 102 may interface with a host system and transmit command sequences for read, program, and erase operations to the non-volatile memory dies 104. Herein, the controller 102 is referred to as a controller die 102 to identify or highlight that the circuitry of the controller 102 is configured or located on a die separate from the plurality of memory dies 104. The controller die 102 and each of the memory dies 104 may be configured or function as transceiver circuits, in that they each can transmit and receive signals. As described in further detail below, the controller die 102 and the plurality of memory dies 104 are configured to communicate with each other over a plurality of transmission lines.	37	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The following embodiments describe systems, apparatuses, devices, circuits, and methods for configuring less than all of a group of dies coupled to a transmission line with a respective on-die termination (ODT) resistance circuit coupled to the transmission line. Before turning to these and other embodiments, the following paragraphs provide a discussion of exemplary memory systems and storage modules that can be used with these embodiments. These are just examples, and other suitable types of systems, apparatuses, devices, or circuits, including other types of memory systems and/or storage modules, can be used.	36	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings.	34	Added by DJM 12 2021	12/22/21, 12:00 AM

Page 5 of 6, showing 20 record(s) out of 103 total