Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	FSP1845	Additionally, the ODT resistance circuit 328 may be configured to change or adjust its resistance from a first resistance level to a second resistance level. The first and second resistance levels may be any of various combinations of high and low resistance levels. That is, depending on the configuration, the ODT resistance circuit 328 may be configured to change its resistance from a high resistance level to a low resistance level, from a low resistance level to a high resistance level, from a first high resistance level of a plurality of high resistance levels to a second high resistance level of the plurality of high resistance levels (where the first high resistance level can be either higher or lower than the second high resistance level), or from a first low resistance level of a plurality of low resistance levels to a second low resistance level of the plurality of low resistance levels (where the first low resistance level can be either higher or lower than the second low resistance level).	95	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The resistance levels that the ODT resistance circuit 328 may be set to may include at least two levels, including a high resistance level and a low resistance level. In addition, for at least some example configurations, the resistance levels may include a plurality of low levels, and/or a plurality of high levels. Accordingly, at a given moment in time, the ODT resistance circuit 328 may be configured to set its resistance to one of a plurality of high resistance levels and/or to set its resistance value to one of a plurality of low resistance levels.	94	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The die group 306 may be configured in any of various ways within the memory system 100. In one example configuration, the die group 306 is configured as a die stack. In general, a given die may be a generally planar structure having two opposing planar surfaces, including a first planar surface and a second planar surface. In a die stack, the dies may be disposed on or "stacked" on top of one another, starting with a first or base die and extending in a direction perpendicular to planar surfaces of the dies. As a die stack, one planar surface of one die may face and/or contact a planar surface of a second die. Also, two dies are adjacent to each other where no other dies of the stack are disposed in between them. Also, in some example configurations, a first or base die may be disposed or mounted on a base substrate or a printed circuit board directly. A last die of the stack may be the die that is disposed furthest from the base substrate or printed circuit board on which the die stack is mounted.	84	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 4 shows a side view of a plurality of dies 402 integrated or configured as a staircase stack. The plurality of dies 402 includes an N-number of memory dies 402(1) to 402(N) that are representative of the N-number memory dies 304(1)-304(N), and an (N+1)th die 402(N+1) that is representative of the end die 310 of the die group 306. The plurality of dies 402 illustrate an example configuration in which the die group 306 may be integrated with each other and the packaging.	86	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	One type of die stack is a staircase stack. In a staircase stack, the dies may be stacked on top of one another such that the dies do not completely cover each other. Instead, each die has an exposed portion where respective I/O contact pads may be disposed and connected with each other via wire bonds. By disposing the dies on top of one another to create exposed portions, the dies of the die stack, when viewed from the side, have a "staircase" shape, which each die being one of the "steps" of the staircase.	85	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the memory die 104 may include peripheral circuitry 150. The peripheral circuitry 150 may include control logic circuitry (otherwise referred to as an on-chip controller, memory die controller, or simply controller) 152, which may be implemented as a state machine, that provides on-chip control of memory operations as well as provide status information to the controller 102. The peripheral circuitry 150 may also include volatile memory 154. An example configuration of the volatile memory 154 may include latches, although other configurations are possible.	66	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.	57	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.	58	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.	59	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.	60	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.	61	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).	62	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in they direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.	63	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additional way of organizing the memory cells of the memory cell structure 142 may be possible. As a non-limiting example, the memory cells may be organized into blocks, and the blocks may be organized into planes. Additionally, the memory cells of the memory cell structure may be connected to biasing lines, including word lines and bit lines. Circuitry on the memory die may be configured to bias the word lines and bit lines with various voltages in order to perform memory operations associated with the memory cells, including read, program, and erase operations.	64	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory die 104 may further include a page buffer or data cache 144 that caches data that is sensed from and/or that is to be programmed to the memory cell structure 142. The memory die 104 may also include a row address decoder 146 and a column address decoder 148. The row address decoder 146 may decode a row address and select a particular wordline in the memory array 142 when reading or writing data to/from the memory cells in the memory array 142. The column address decoder 148 may decode a column address to select a particular group of bitlines in the memory array 142 to be electrically coupled to the data cache 144.	65	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	With respect to the packaging components and/or the transmission line 308, the die group 306 includes those dies that are mounted on the same die substrate 302, housed within the same outer encasing 312, and/or have I/O contact pads 322 coupled to wire bonds 320 that are connected in series from the packaging portion 318 to the (N+1)th I/O contact pad 316(N+1) of the end die 310.	81	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, the memory die 104 may include a memory-side memory interface (or just memory-side interface) 156 that is configured to interface and communicate with the controller-side memory interface 130 of the controller die 102. In particular, the memory-side interface 156 may be coupled with the transmission lines 134 of the memory system 100. When a given memory die 104 is to transmit a signal to the controller die 102, the given memory die 104 may transmit the signal via its memory-side interface 156 onto one of the transmission lines 134 to the controller die 102. Additionally, when a given memory die 104 is to receive a signal from the controller die 102, the given memory die 104 may receive the signal via its memory-side interface 156 from one of the transmission lines 134. As described in further detail below, components of the memory-side interface 156, along with die capacitance of the dies may form part of and/or determine characteristics impedances of the transmission lines 134.	67	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory-side interface 156 may include memory input/output (I/O) circuitry 158 that is configured to send, receive, and generate signals, including data signals carrying data, command signals identifying commands, clock signals, or other types of signals carrying other information to be transmitted to and received from the controller die 102. For example, data sensed into the data cache 144 may be sent to the memory I/O circuitry 158 for transmission to the controller die 102. Similarly, data received from the controller die 102 may be received by the memory I/O circuitry 158, and the memory I/O circuitry 158 may communicate the data to the data cache 144. Additionally, commands to be communicated between the controller die 102 and the control logic 152 may be communicated via the memory I/O circuitry 158. The memory I/O circuitry 158 may be configured similar to and/or have similar or the same circuit topologies have any of various circuit or combinations of circuits, including output driver circuits, such as in the form of push-pull circuits, to generate and output signals onto the transmission lines 134, and input buffers, such as in the form of comparators and/or Schmitt trigger circuits to receive signals on the transmission lines 134. Any of various suitable circuit configurations to transmit, receive, and generate signals and connect to the transmission lines 134 to communicate the signals may be possible.	68	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the memory-side interface 156 may include input/output (I/O) contact pad portions 160 in communication with the memory I/O circuitry 158. For example, the signals that the memory I/O circuitry 158 generates for transmission to the controller die 102 may be communicated from the output driver circuits of the memory I/O circuitry 158 to the I/O contact pads 160. Similarly, the signals that the memory-side interface 156 receives from the controller die 102 may be sent from the I/O contact pads 160 to input circuits (e.g., input buffer circuits) of the memory I/O circuitry 158. In addition, as described in further detail below, the I/O contact pads 160, along with wire bond elements (WBE) (shown in FIG. 3) may form or be part of the transmission lines 134 over which the memory dies 104 and the controller die 102 communicate signals between each other.	69	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, in at least some embodiments, as shown in FIG. 2B, the memory-side interface 156 may include on-die termination (ODT) resistance circuitry 162, which may include one or more resistors or other circuit components (active and/or passive) providing a resistance. The on-die termination resistance circuitry 162 may provide termination resistance or impedance for the transmission lines 134, and may be used for impedance matching between the memory dies 104 and the transmission lines 134. The on-die termination resistance circuitry 162 may be connected to the I/O contact pads 160. In addition, for at least some embodiments, the on-die termination resistance circuitry 162 may provide variable resistance levels or values, including one or more high levels and one or more low levels, as described in further detail below. The resistance levels or values that the on-die termination resistances provide may be controlled by the controller die 102, the on-die control logic 152, or a combination thereof.	70	Added by DJM 12 2021	12/22/21, 12:00 AM

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