Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	FSP1845	Additional way of organizing the memory cells of the memory cell structure 142 may be possible. As a non-limiting example, the memory cells may be organized into blocks, and the blocks may be organized into planes. Additionally, the memory cells of the memory cell structure may be connected to biasing lines, including word lines and bit lines. Circuitry on the memory die may be configured to bias the word lines and bit lines with various voltages in order to perform memory operations associated with the memory cells, including read, program, and erase operations.	64	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory die 104 may further include a page buffer or data cache 144 that caches data that is sensed from and/or that is to be programmed to the memory cell structure 142. The memory die 104 may also include a row address decoder 146 and a column address decoder 148. The row address decoder 146 may decode a row address and select a particular wordline in the memory array 142 when reading or writing data to/from the memory cells in the memory array 142. The column address decoder 148 may decode a column address to select a particular group of bitlines in the memory array 142 to be electrically coupled to the data cache 144.	65	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the memory die 104 may include peripheral circuitry 150. The peripheral circuitry 150 may include control logic circuitry (otherwise referred to as an on-chip controller, memory die controller, or simply controller) 152, which may be implemented as a state machine, that provides on-chip control of memory operations as well as provide status information to the controller 102. The peripheral circuitry 150 may also include volatile memory 154. An example configuration of the volatile memory 154 may include latches, although other configurations are possible.	66	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, the memory die 104 may include a memory-side memory interface (or just memory-side interface) 156 that is configured to interface and communicate with the controller-side memory interface 130 of the controller die 102. In particular, the memory-side interface 156 may be coupled with the transmission lines 134 of the memory system 100. When a given memory die 104 is to transmit a signal to the controller die 102, the given memory die 104 may transmit the signal via its memory-side interface 156 onto one of the transmission lines 134 to the controller die 102. Additionally, when a given memory die 104 is to receive a signal from the controller die 102, the given memory die 104 may receive the signal via its memory-side interface 156 from one of the transmission lines 134. As described in further detail below, components of the memory-side interface 156, along with die capacitance of the dies may form part of and/or determine characteristics impedances of the transmission lines 134.	67	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory-side interface 156 may include memory input/output (I/O) circuitry 158 that is configured to send, receive, and generate signals, including data signals carrying data, command signals identifying commands, clock signals, or other types of signals carrying other information to be transmitted to and received from the controller die 102. For example, data sensed into the data cache 144 may be sent to the memory I/O circuitry 158 for transmission to the controller die 102. Similarly, data received from the controller die 102 may be received by the memory I/O circuitry 158, and the memory I/O circuitry 158 may communicate the data to the data cache 144. Additionally, commands to be communicated between the controller die 102 and the control logic 152 may be communicated via the memory I/O circuitry 158. The memory I/O circuitry 158 may be configured similar to and/or have similar or the same circuit topologies have any of various circuit or combinations of circuits, including output driver circuits, such as in the form of push-pull circuits, to generate and output signals onto the transmission lines 134, and input buffers, such as in the form of comparators and/or Schmitt trigger circuits to receive signals on the transmission lines 134. Any of various suitable circuit configurations to transmit, receive, and generate signals and connect to the transmission lines 134 to communicate the signals may be possible.	68	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the memory-side interface 156 may include input/output (I/O) contact pad portions 160 in communication with the memory I/O circuitry 158. For example, the signals that the memory I/O circuitry 158 generates for transmission to the controller die 102 may be communicated from the output driver circuits of the memory I/O circuitry 158 to the I/O contact pads 160. Similarly, the signals that the memory-side interface 156 receives from the controller die 102 may be sent from the I/O contact pads 160 to input circuits (e.g., input buffer circuits) of the memory I/O circuitry 158. In addition, as described in further detail below, the I/O contact pads 160, along with wire bond elements (WBE) (shown in FIG. 3) may form or be part of the transmission lines 134 over which the memory dies 104 and the controller die 102 communicate signals between each other.	69	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, in at least some embodiments, as shown in FIG. 2B, the memory-side interface 156 may include on-die termination (ODT) resistance circuitry 162, which may include one or more resistors or other circuit components (active and/or passive) providing a resistance. The on-die termination resistance circuitry 162 may provide termination resistance or impedance for the transmission lines 134, and may be used for impedance matching between the memory dies 104 and the transmission lines 134. The on-die termination resistance circuitry 162 may be connected to the I/O contact pads 160. In addition, for at least some embodiments, the on-die termination resistance circuitry 162 may provide variable resistance levels or values, including one or more high levels and one or more low levels, as described in further detail below. The resistance levels or values that the on-die termination resistances provide may be controlled by the controller die 102, the on-die control logic 152, or a combination thereof.	70	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 3 shows a physical layout of an example configuration of at least some of the components of the controller die 102 and the plurality of memory dies 104 shown in FIGS. 1A-2B. In FIG. 3, at least some of the memory dies 104 are represented by an N-number memory dies 304, including a first memory die 304(1), a second memory die 304(2), and an Nth memory die 304(N). In various embodiments, N may be any integer of two or more. The N-number of memory dies 304(1)-304(N) may be all of the memory dies 104 in the memory system 100, or may be less than all of the memory dies 104. For example, the N-number of memory dies 304(1)-304(N) may be located on the same chip and/or may be part of the same chip enable group. The memory system 100 may include a single chip or chip enable group in which the memory dies 104 are located. The N-number of memory dies 304 of FIG. 3 may be representative of that single chip or chip enable group of dies. Alternatively, the memory system 100 may include multiple chips or chip enable groups, and some of the memory dies 104 may be located on one chip or in one chip enable group, while other memory dies 104 may be located on one or more other chips or in one or more other chip enable groups. The N-number of memory dies 304 of FIG. 3 may be representative of one of the plurality of chips or chip enable groups. In addition or alternatively, the N-number of memory dies 304 may be configured as or part of the same die stack. Various configurations are possible. Further details of dies configured as a die stack are described in further detail below with reference to FIG. 4.	71	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the memory dies 304 may be part of a group of dies (or die group) 306 that further includes an end (or termination) die 310. The end die 310 is described in further detail below.	72	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In the example configuration shown in FIG. 3, the group of dies 306, including the memory dies 304 and the end die 310, may be configured in and/or integrated with a packaging that includes various packaging components, including a package or die substrate 302 on which the die group 306 is disposed or mounted, and an outer encasing or cover 312 that encases, covers, houses, and/or protects the dies of the die group 306. Other packaging components may be included, such as traces and vias integrated in the die substrate 302, solder balls, contact pads, and/or wire bonds, as non-limiting examples, at least some of which are described in further detail below. The controller die 102 may be configured and/or implemented as its own chip and/or integrated with its own packaging separate to that of the die group 306. (For simplicity, packaging components of the controller die 102 are not shown in FIG. 3). The controller die 102 and the die group 306 integrated with the packaging may be integrated, mounted, or disposed on a printed circuit board 314, as shown in FIG. 3.	73	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller die 102 and the memory dies 304(1)-304(N) may communicate signals between each other on transmission lines (e.g., at least some of the transmission lines 134 of FIGS. 2A and 2B) connecting the controller die 102 and the memory dies 304(1)-304(N). For simplicity, the physical layout of FIG. 3 shows a single transmission line 308 connecting the controller die 102 and the memory dies 304. However, in actual implementation as described with reference to FIGS. 2A and 2B, there may be multiple transmission lines between the controller 102 and the memory dies 304(1)-304(N) configured to communicate data signals, clock signals, strobe signals, command signals, status signals, or any other type of signals between the controller die 102 and the memory dies 304. The multiple (at least two) transmission lines may be configured in parallel with each other such that two or more signals propagating on two or more parallel transmission lines may be communicated separately and/or simultaneously.	74	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the transmission line 308 may be a unidirectional transmission line or a bidirectional transmission line. A unidirectional line is a transmission line that is configured to communicate signals one way or in one direction, either only from the controller die 102 to the memory dies 304, or only from the memory dies 304 to the controller die 102. In contrast, a bidirectional line is a transmission line that is configured to communicate signals both ways or in both directions, from the controller die 102 to the memory dies 304, and from the memory dies 304 to the controller die 102. For configurations that include multiple transmission lines, in various embodiments, all of the transmission lines may be unidirectional lines, all of the transmission lines may bidirectional lines, or the transmission lines may include a combination of at least one unidirectional line and at least one bidirectional line. Various configurations of unidirectional and/or bidirectional transmission lines may be possible.	75	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, for some example configurations, the transmission line 308 may be configured as a single-ended transmission line or signal path configured to communicate a single-ended signal. For such configurations, the single-ended transmission line 308 may be electrically coupled to a ground reference or return path (not shown in FIG. 3). For other example configurations, the transmission line 308 may be one of the conductive paths of a differential transmission line or signal path configured to communicate a differential signal. As described in further detail below, the transmission line 308 may include any of various types of conductive elements, such as traces, vias, solder balls, contact pads, and wire bonds, as non-limiting examples, to communicate a signal between the controller 102 and the memory dies 304.	76	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the transmission line 308, whether it be for a single-ended configuration or a differential configuration, may include a printed circuit board (PCB) portion 316, a packaging portion 318, a wire bond portion 320, and an input/output (I/O) contact pad portion 322.	77	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The PCB portion 316 may be integrated with the printed circuit board 314 and extend between the controller die 102 and the memory die packaging. In addition, the PCB portion 316 may be implemented as a conductive trace (such as in the form of a microstrip or a stripline, for example), one or more vias, any other type of conductive element, or combinations thereof, configured to carry a signal over the printed circuit board 314 from the controller die 102 to the memory die packaging.	78	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the packaging portion 318 of the transmission line 308 may be configured to communicate signals between the PCB signal portion 316 and the wire bond portion 320. The packaging portion 318 may include a first packaging contact point 324 that connects to the PCB portion 316 in order to communicate signals between the PCB portion 316 and the packaging portion 318, and a second packaging contact point 326 that connects to the wire bond portion 320 in order to communicate signals between the packaging portion 318 and the wire bond portion 320. The packaging portion 318, including the first and second contact points 324, 326, may include any of various conductive elements and/or combinations of conductive elements to communicate signals between the PCB portion 316 and the wire bond portion 320, examples of which include solder balls, such as those of a ball grid array structure, vias, and/or traces integrated in the die substrate 302, contact pads, and wire bonds. Various configurations of the packaging portion 318 for connecting the PCB portion 316 with the wire bond portion 320 are possible.	79	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the wire bond portion 320 may include an (N+1)-number of wire bond elements (WBE) (or just wire bonds) 320(1) to 320(N+1), and the I/O contact pad portion 322 may include an (N+1)-number of I/O contact pads 322(1) to 322(N+1). Each of the I/O contact pads 322 may be integrated with, such as by being disposed on, a respective one of the memory dies 304 or the end die 310 of the die group 306. For at least some example configurations, such as the one shown in FIG. 3, a first wire bond 320(1) includes a first end connected to the second packaging contact point 326 and a second end connected to the I/O contact pad 322(1) of the first memory die 304(1). The other wire bond elements of the wire bond portion 320 may have each of the ends connected to an I/O contact pad of two different dies of the die group 306. For example, as shown in FIG. 3, a second wire bond 320(2) has a first end connected to the I/O contact pad 322(1) of the first memory die 304(1) and a second end connected to the I/O contact pad 322(2) of the second memory die 304(2); a third wire bond 320(3) has a first end connected to the I/O contact pad 322(2) of the second memory die 304(2) and a second end connected to the I/O contact pad 322(3) of a third memory die 304(3) (not shown); an Nth wire bond 320(N) has a first end connected to an I/O contact pad 322(N-1) of an (N-1)th memory die 304(N-1) (not shown) and a second end connected to an I/O contact pad 322(N) of the Nth memory die 304(N); and an (N+1)th wire bond 320(N) has a first end connected to the I/O contact pad 322(N) of the Nth memory die 304(N) and a second end connected to the I/O contact pad 322(N+1) of the end die 310.	80	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	With respect to the packaging components and/or the transmission line 308, the die group 306 includes those dies that are mounted on the same die substrate 302, housed within the same outer encasing 312, and/or have I/O contact pads 322 coupled to wire bonds 320 that are connected in series from the packaging portion 318 to the (N+1)th I/O contact pad 316(N+1) of the end die 310.	81	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The wire bonds 320 and the I/O contact pads 322, in combination, may form a part or a portion of the transmission line 308, with each wire bond 320 and each I/O contact pad 322 having positions relative to each other in the transmission line 308 that correspond to propagation delay or electrical distance from the packaging portion 318. A signal transmitted from the controller die 102 on the transmission line 308 may take a shorter amount of time to reach a given I/O contact pad 322 or a given wire bond element 320 that is positioned electrically closer to the packaging portion 318, compared to a given I/O contact pad or a given wire bond element positioned electrically farther from the packaging portion 318, along the transmission line 308.	82	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory dies 304, the wire bond elements 320, and the I/O contact pad 322 are numbered in FIG. 3 to correspond to their respective positions in the transmission line 308. Given an index k, the higher the value of k, the further away a kth memory die 304(k), a kth wire bond element 314(k), and/or a kth I/O contact pad 316(k) are electrically along the transmission line 308 from the packaging portion 318, the PCB portion 316, and the controller die 102. In this context, the (N+1)th I/O contact pad 322(N+1) is the electrically furthest of the I/O contact pads 322 along the transmission line 308 from the packaging portion 318, the PCB portion 316, and/or the controller die 102, and, in turn, is or functions as a memory-side end or termination of the transmission line 308. In this context, the end die 310 is the die that is the furthest of the dies of the die group 306 from the packaging portion 318, the PCB portion 316, and/or the controller die 102 with reference to the transmission line 308. In addition or alternatively, the end die 310 is the die that includes the (N+1)th I/O contact pad 322(N+1) that functions as the memory-side end or termination of the transmission line 308.	83	Added by DJM 12 2021	12/22/21, 12:00 AM

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