Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	US10998041B1	In certain embodiments, data stored in non-volatile memory media is addressable at a block level which means that the data in the non-volatile memory media is organized into data blocks that each have a unique logical address (e.g., LBA). In other embodiments, data stored in non-volatile memory media is addressable at a byte level which means that the data in the non-volatile memory media is organized into bytes (8 bits) of data that each have a unique address, such as a logical address. One example of byte addressable non-volatile memory media is storage class memory (SCM).	41	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In some embodiments, each storage device 200 may include two or more memory dies 104, such as flash memory, nano random-access memory ("nano RAM or NRAM"), magneto-resistive RAM ("MRAM"), dynamic RAM ("DRAM"), phase change RAM ("PRAM"), etc. In further embodiments, the data storage device 200 may include other types of non-volatile and/or volatile data storage, such as dynamic RAM ("DRAM"), static RAM ("SRAM"), magnetic data storage, optical data storage, and/or other data storage technologies.	42	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The storage device 200 may be a component within a host 106 as depicted in here, and may be connected using a data bus 112, such as a peripheral component interconnect express ("PCI-e") bus, a Serial Advanced Technology Attachment ("serial ATA") bus, or the like. In another embodiment, the storage device 200 is external to the host 106 and is connected, a universal serial bus ("USB") connection, an Institute of Electrical and Electronics Engineers ("IEEE") 1394 bus ("FireWire"), or the like. In other embodiments, the storage device 200 is connected to the host 106 using a peripheral component interconnect ("PCI") express bus using external electrical or optical bus extension or bus networking solution such as InfiniBand or PCI Express Advanced Switching ("PCIe-AS"), or the like.	43	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In various embodiments, the storage device 200 may be in the form of a dual-inline memory module ("DIMM"), a daughter card, or a micro-module. In another embodiment, the storage device 200 is a component within a rack-mounted blade. In another embodiment, the storage device 200 is contained within a package that is integrated directly onto a higher-level assembly (e.g., mother board, laptop, graphics processor). In another embodiment, individual components comprising the storage device 200 are integrated directly onto a higher-level assembly without intermediate packaging. The storage device 200 is described in further detail with regard to FIG. 2.	44	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Processor" refers to any circuitry, component, chip, die, package, or module configured to receive, interpret, decode, and execute machine instructions. Examples of a processor may include, but are not limited to, a central processing unit, a general-purpose processor, an application-specific processor, a graphics processing unit (GPU), a field programmable gate array (FPGA), Application Specific Integrated Circuit (ASIC), System on a Chip (SoC), virtual processor, processor core, and the like.	45	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Circuitry" refers to electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes or devices described herein), circuitry forming a memory device (e.g., forms of random access memory), or circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment).	46	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In a further embodiment, instead of being connected directly to the host 106 as DAS, the data storage device 200 may be connected to the host 106 over a data network. For example, the data storage device 200 may include a storage area network ("SAN") storage device, a network attached storage ("NAS") device, a network share, or the like. In one embodiment, the storage system 100 may include a data network, such as the Internet, a wide area network ("WAN"), a metropolitan area network ("MAN"), a local area network ("LAN"), a token ring, a wireless network, a fiber channel network, a SAN, a NAS, ESCON, or the like, or any combination of networks. A data network may also include a network from the IEEE 802 family of network technologies, such Ethernet, token ring, Wi-Fi, Wi-Max, and the like. A data network may include servers, switches, routers, cabling, radios, and other equipment used to facilitate networking between the host 106 and the data storage device 200.	47	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The storage system 100 includes at least one host 106 connected to the storage device 200. Multiple hosts 106 may be used and may comprise a server, a storage controller of a storage area network ("SAN"), a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, router, or appliance, a database or storage appliance, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, or the like. In another embodiment, a host 106 may be a client, and the storage device 200 may operate autonomously to service data requests sent from the host 106. In this embodiment, the host 106 and storage device 200 may be connected using a computer network, system bus, Direct Attached Storage (DAS), or other communication means suitable for connection between a computer and an autonomous storage device 200.	48	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The depicted embodiment shows a user application 108 in communication with a storage client 110 as part of the host 106. In one embodiment, the user application 108 is a software application operating on or in conjunction with the storage client 110. "Storage client" refers to any hardware, software, firmware, or logic component or module configured to communicate with a storage device in order to use storage services. Examples of a storage client include, but are not limited to, operating systems, file systems, database applications, a database management system ("DBMS"), server applications, a server, a volume manager, kernel-level processes, user-level processes, applications, mobile applications, threads, processes, and the like.	49	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In general, a high resistance level is higher than a low resistance level. In some example configurations, the high resistance level, is greater than or equal to 500 Ohms (.OMEGA.) and the low resistance level is lower than or equal to 100.OMEGA.. Example high resistance levels may be 500 Ohms, 1 k.OMEGA., or 10 k.OMEGA. Example low resistance levels include 10 Ohms, 25 Ohms, 35 Ohms, 50 Ohms, 75 Ohms, and 100 Ohms. Other high and/or low resistance levels may be possible. In addition or alternatively, the high resistance level may be greater than or equal to ten times a characteristic impedance of the transmission line 308.	96	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, for some example configurations the high resistance level is a single or fixed value, and the low resistance level can be any one of a plurality of low resistance levels at any given moment in time. For such configurations, each of the low resistance levels is lower than the single high resistance level. For other example configurations, the low resistance level is a single or fixed value, and the high resistance level can be any one of a plurality of high resistance levels at any given moment in time. For such configurations, each of the high resistance levels is higher than the single low resistance levels. For still other example configurations, at any given moment in time, the high resistance level may be any one of a plurality of high resistance levels and the low resistance level may be any one of a plurality of low resistance levels. For such configurations, all of the high resistance levels are higher than all of the low resistance levels.	97	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, in some example configurations, at a given point in time, the ODT resistance circuit 328 may set its resistance level to a high resistance level that is in a range of high resistance levels that includes an upper bound high resistance level and a lower bound high resistance level, and/or may set its resistance level to a low resistance level that is in a range of low resistance levels that includes an upper bound low resistance level and a lower bound low resistance level. At any given point in time, the ODT resistance circuit 328 may set its resistance to any one of a plurality of high resistance levels in the range of high resistance levels, and/or may set its resistance level to any one of a plurality of low resistance levels in the range of low resistance levels. In addition or alternatively, the resistance levels may be discrete values or levels, and the ODT resistance circuit 328 may set its resistance level to one of the discrete resistance levels. In particular example configurations, the discrete levels may form or determine a range of high resistance levels or a range of low resistance levels. To illustrate, suppose for example that at any given moment in time, the ODT resistance circuit 328 is configured to set its resistance to a high resistance level that may be any one of a plurality of predetermined or discrete high resistance levels, including 500 .OMEGA., 1 k.OMEGA., or 10 k.OMEGA. Accordingly, the resistance levels of 500 .OMEGA., 1 k.OMEGA., and 10 k.OMEGA. may determine a high resistance level range, where 10 k.OMEGA. is the upper bound of the range and 500.OMEGA. is the lower bound of the range. As another illustration, suppose for example that at any given moment in time, the ODT resistance circuit 328 is configured to set its resistance to a low resistance level that may be any one of a plurality of predetermined or discrete low resistance levels, including 10 .OMEGA., 35.OMEGA., and 50.OMEGA.. Accordingly, the resistance levels of 10 .OMEGA., 35.OMEGA., and 50.OMEGA. may determine a low resistance level range, where 50.OMEGA. is the upper bound of the range and 10.OMEGA. is the lower bound of the range.	98	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	For simplicity, as used hereafter and unless expressly specified otherwise, the ODT resistance circuit 328 being at, set to, and/or adjusted to a low level may mean that the ODT resistance circuit 328 is at, set to, and/or adjusted to a resistance level that is lower than the high resistance value or a lowest of a plurality of high resistance levels to which the ODT resistance circuit 328 may be set, which may not necessarily be an absolute low level. Similarly, the ODT resistance circuit 328 being at, set to, and/or adjusted to a high level may mean that the ODT resistance circuit 328 is at, set to, and/or adjusted to a resistance level that is higher than the low resistance value or a highest of a plurality of low resistance levels to which the ODT resistance circuit 328 may be set, which may not necessarily be an absolute high level.	99	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The resistance level that the ODT resistance circuit 328 provides may be determined and/or controlled by the controller die 102, the end die 310 itself, such as by their on-die control circuits 152 (FIG. 2B), or a combination thereof. As shown in FIG. 3, the ODT resistance circuits 328 may be configured to receive a control signal CTRL that sets and/or adjusts the resistance level. For some example configurations, the controller die 102 may send a command signal to the plurality of memory dies 304 that indicates one or more resistance levels of the ODT resistance circuit 328. In response, the end die 310 may set the ODT resistance circuit 328 to the resistance level indicated by the command signal. For example, the on-die control circuit 152 of the end die 310 may output the control signal CTRL to the ODT resistance circuit 328.	100	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the ODT resistance circuit 328 may be part of or coupled to the transmission line 308. In particular, the ODT resistance circuit 328 may be and/or referred to as a dedicated end-die termination resistance circuit 328 that provides an end or termination resistance of the transmission line 328. The end or termination resistance provided by the dedicated end-die termination resistance circuit 328 may be also be referred to as a memory-side end or termination resistance, as opposed to a controller-side end or termination resistance that the controller die 102 provides.	101	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In various embodiments, none, or at least one, of the memory dies 304 similarly includes an ODT resistance circuit, like the ODT resistance circuit 328 of the end die 310, such that an M-number of dies of the die group 306 that includes an ODT resistance circuit coupled to the transmission line 308 is less than the total N+1 number of dies of the die group 306. Accordingly, at least one of the dies of the group 306 does not include an ODT resistance circuit connected to its I/O contact pad forming part of the transmission line 308. In particular example embodiments, such as the one shown in FIG. 3, only the end die 310 has its ODT resistance circuit 328, and the other dies of the die group--i.e., all of the N-number of memory dies 304(1) to 304(N)--are configured without ODT resistance circuits coupled to the transmission line 308. In other example embodiments, in addition to the end die 310, at least one but less than all of the memory dies 304 includes an ODT resistance circuit coupled to the transmission line 308. For example, FIG. 6 shows an alternative die group 602, where the Nth memory die 304(N) includes an ODT resistance circuit 604 coupled to its I/O contact pad 322(N), like the end die 310.	102	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In general, an ODT resistance circuit may include one or more resistors in combination with one or more transistors (switches) to provide a variable resistance, such as at one or more high resistance levels and/or one or more low resistance levels, as previously described. Such circuit components cause the ODT resistance circuit to have an associated capacitance, which adds to the die capacitance of the die in which the ODT resistance circuit is configured, increasing an effective die (or parasitic) capacitance that contributes to the characteristic impedance of the transmission line 308 over the wire bond portion 320. The higher the effective die capacitance, the more limited the frequency, bandwidth, or data rate at which signals can be transmitted over the transmission line 308 with sufficient quality.	103	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In other example embodiments, all of the dies of the die group 306--i.e., all of the memory dies 304 and the end die 310--are configured with an ODT resistance circuit. While these embodiments may be optimal from a manufacturing perspective since all of the dies have the same ODT configuration, such embodiments provide a less than optimal effective die capacitance for the transmission line 308. In contrast, reducing the number of dies of the die group 306 that has an ODT resistance circuit coupled to the transmission line 308 reduces the effective die capacitance. To illustrate, for a die group that includes 16 dies, configuring only the end die with a termination resistance circuit may reduce the effective die (or parasitic) capacitance by over 30% (e.g., from 2.4 picoFarads (pF) to 1.8 pF, in some embodiments). The reduction in capacitance, in turn, allows for increased frequency, bandwidth, and/or data rate at which signals can be transmitted over the transmission line 308 without degrading the quality of the transmissions below acceptable levels.	104	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, die group configurations where none of the dies include an ODT resistance circuit may be less than optimal since none of the dies of the die group can terminate the transmission line with a termination resistance at a low level. In turn, the transmission line 308 is limited in terms of the frequency, bandwidth, and/or data rate of the signals that it can transmit with sufficient quality. Accordingly, configuring at least one of the dies of the die group 306, such as the end die 310, with an ODT resistance circuit, while configuring at least one of the other dies without an ODT resistance circuit, may provide an optimal combination of dies with and without ODT resistance circuits that desirably terminates the transmission line 308 with a low resistance level at the memory side while reducing the effective die capacitance, which in turn allows for signals to be communicated over the transmission line 308 between the controller die 102 and the die group 306 at higher frequencies, bandwidth, and/or data rates.	105	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Also, by reducing the number of dies of the die group 306 that includes an ODT resistance circuit, power consumption may be reduced. The number of commands communicated over the transmission lines 134 to set the ODT resistances to the die group 306 may also be reduced, simplifying the overall process to set ODT resistance for communication between the controller die 102 and the die group 306.	106	Added by DJM 12 2021	12/22/21, 12:00 AM

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