Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	FSP1845	In some embodiments, the die stack comprises a staircase stack.	19	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the group of dies is configured to communicate over the transmission line at a predetermined high frequency and at a predetermined low frequency, and wherein the on-die termination resistance circuit is configured to: set an associated resistance at a low level when the group of dies communicates over the transmission line at the predetermined high frequency; and set the associated resistance at a high level when the group of dies communicates over the transmission line at the predetermined low frequency.	20	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In other embodiment, an apparatus includes: a controller die, and a group of dies configured to communicate with the controller die via a transmission line, wherein the group of dies comprises a plurality of memory dies and an end die. The group of dies includes at least one on-die termination circuit coupled to the transmission line. Additionally, less than all of the group of dies comprises a respective one of the at least one on-die termination circuit.	21	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, only one of the dies of the group comprises the at least one on-die termination circuit coupled to the transmission line.	22	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the only one of the dies comprises the end die.	23	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the end die is configured to store data.	24	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the end die is configured to perform error correction.	25	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the end die does not include additional circuitry other than input/output contact pads and on-die resistance circuits.	26	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the controller die and the group of dies are configured to communicate over the transmission line at a predetermined high frequency and at a predetermined low frequency. The at least one on-die termination resistance circuit is configured to: set an associated resistance at a low level for communication over the transmission line at the predetermined high frequency, and set the associated resistance at a high level for communication over the transmission line at the predetermined low frequency.	30	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In another embodiment, a method includes: setting an on-die termination resistance circuit of an end die of a group of dies to a low level, where the on-die termination resistance circuit is coupled to a transmission line, and where no other dies of the group of dies comprises a respective on-die termination resistance circuit; and communicating a signal over the transmission line between the group of dies and a controller die with the on-die termination resistance circuit set to the low level.	31	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, communicating the signal comprises communicating the signal at a predetermined high frequency, and setting the on-die termination resistance circuit to the low level is dependent on communicating the signal at the predetermined high frequency.	32	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the method includes: setting the on-die termination resistance circuit of the end die to a high level dependent on communicating a second signal over the transmission line at a predetermined low frequency; and communicating the second signal over the transmission line between the group of dies and the controller die with the on-die termination resistance circuit set to the high level.	33	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings.	34	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The following embodiments describe systems, apparatuses, devices, circuits, and methods for configuring less than all of a group of dies coupled to a transmission line with a respective on-die termination (ODT) resistance circuit coupled to the transmission line. Before turning to these and other embodiments, the following paragraphs provide a discussion of exemplary memory systems and storage modules that can be used with these embodiments. These are just examples, and other suitable types of systems, apparatuses, devices, or circuits, including other types of memory systems and/or storage modules, can be used.	36	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1A is a block diagram illustrating a memory system 100, such as a non-volatile memory system. The memory system 100 may include a controller 102 and memory that may be made up of a plurality of memory dies 104. As used herein, the term memory die refers to the set of memory cells (including non-volatile memory cells), and associated circuitry for managing the physical operation of those memory cells, that are formed on a single semiconductor substrate. In addition, the term die, in general, may refer to circuitry or circuit components on a single semiconductor substrate, but may or may not include memory cells to store data. The controller 102 may interface with a host system and transmit command sequences for read, program, and erase operations to the non-volatile memory dies 104. Herein, the controller 102 is referred to as a controller die 102 to identify or highlight that the circuitry of the controller 102 is configured or located on a die separate from the plurality of memory dies 104. The controller die 102 and each of the memory dies 104 may be configured or function as transceiver circuits, in that they each can transmit and receive signals. As described in further detail below, the controller die 102 and the plurality of memory dies 104 are configured to communicate with each other over a plurality of transmission lines.	37	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller die 102 can take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example. The controller die 102 can be configured with hardware and/or firmware to perform the various functions described below. Also, some of the components shown as being internal to the controller die 102 can also be stored external to the controller die 102, and other components can be used. Additionally, the phrase "operatively in communication with" could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein.	38	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller die 102 is configured to manage data stored in memory cells of the memory dies 104 and also to communicate with a host, such as a computer or electronic device. The controller die 102 can have various functionality in addition to the specific functionality described herein. For example, the controller die 102 can format the memory cells and/or the circuitry of the memory dies 104 to ensure the memory dies 104 operate properly, map out bad or defective memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the controller die 102 and implement other features. In operation, when a host needs to read data from or write data to the memory die 104, the host communicates with the controller die 102. If the host provides a logical address to which data is to be read/written, the controller die 102 can convert the logical address received from the host to a physical address in the memory dies 102. (Alternatively, the host can provide the physical address). The controller die 102 may also be configured to perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused).	39	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The interface between the controller die 102 and the memory dies 104 may be any suitable memory interface, such as Toggle Mode 200, 400, or 800. In one embodiment, the memory system 100 may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, the system 100 may be part of an embedded memory system.	40	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1B illustrates a storage module 200 that includes a plurality of memory systems 100. As such, the storage module 200 may include a storage controller 202 that interfaces with a host and with a storage system 204, which includes a plurality of memory systems 100. The interface between the storage controller 202 and memory systems 100 may be a bus interface, such as a serial advanced technology attachment (SATA), a serial attached SCSI (SAS), a peripheral component interface express (PCIe) interface, an embedded MultiMediaCard (eMMC) interface, a SD interface, or a Universal Serial Bus (USB) interface, as non-limiting examples. The storage system 200, in one embodiment, may be a solid state drive (SSD), such as found in portable computing devices, such as laptop computers and tablet computers, and mobile phones.	41	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 2A is a block diagram illustrating exemplary components of the controller die 102 in more detail. The controller die 102 may include a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the memory dies 104, and various other modules that perform various functions of the memory system 100. In general, a module may be hardware or a combination of hardware and software. For example, each module may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. In addition or alternatively, each module may include memory hardware that comprises instructions executable with a processor or processor circuitry to implement one or more of the features of the module. When any one of the module includes the portion of the memory that comprises instructions executable with the processor, the module may or may not include the processor. In some examples, each module may just be the portion of the memory that comprises instructions executable with the processor to implement the features of the corresponding module without the module including any other hardware. Because each module includes at least some hardware even when the included hardware comprises software, each module may be interchangeably referred to as a hardware module.	43	Added by DJM 12 2021	12/22/21, 12:00 AM

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