Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	FSP1845	In various example methods of operation, when the controller die 102 and the memory dies 304 communicate with each other over the transmission line 308--either by the controller die 102 transmitting a signal over the transmission line 308 to the memory dies 304, or one of the memory dies 304 transmitting a signal over the transmission line 308 to the controller die 102--the ODT resistance circuit 328 is set to the low resistance level. In some embodiments, the controller die 102 and the memory die 304 may be configured to communicate with each other over the transmission line 308 at different frequencies, including a high frequency and a low frequency. The high frequency and the low frequency may be predetermined values, where, in general, the high frequency is a higher value than the low frequency. During communication over the transmission line 308, whether the ODT resistance circuit 328 is set to the high level or the low level may depend on whether signal communicated over the transmission line is communicated at the high frequency or the low frequency. For such embodiments, when the controller die 102 and the memory dies 304 communicate at the high frequency, the end die 310 has the ODT resistance circuit 328 set to the low resistance level. Alternatively, when the controller die 102 and the memory dies 304 communicate at the low frequency, the end die 310 has the ODT resistance circuit 328 set to the high resistance level.	107	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some example embodiments, the end die 310 is a "dummy" die for the die group 306, in that it only has I/O contact pads and ODT resistance circuits coupled to the transmission lines 134, and/or its sole function is to provide memory-side termination resistances for the transmission lines 134. For other example embodiments, such as the one shown in FIG. 3, the end die 310 includes additional circuitry 330--i.e., in addition to I/O contact pads and ODT resistance circuits. The additional circuitry 330 may be configured to perform one or more functions for the memory system 100 other than provide a memory-side termination resistance for the transmission lines 134. For example, in some example embodiments, the end die 310 is another one of the memory dies 104, configured to store data, like the memory dies 304. Accordingly, the additional circuitry 330 includes at least some of the components of the memory die 104 shown in FIG. 2B. In other example embodiments, the additional circuitry 330 includes error correction circuitry that is configured to detect and/or correct for errors in signals communicated over the transmission lines 134, and/or perform diagnostics such as parity checks or bit error rate estimation. Other types of additional circuitry 330, and/or functions other than those for storing data, performing error correction or detection, or other diagnostics, may be possible.	108	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, in various example embodiments, the end die 310 may be the same size as the memory dies 304, or may have a smaller size than the memory dies 304. In particular embodiments, the end die 310 may be a smaller die where the end die is not also a memory die, and in turn does not require as large of a size as the memory dies 304. A smaller die may desirably reduce the size and/or cost associated with the die group 306.	109	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	A memory system may communicate signals carrying data, command, or clocking information for the storage of data within the memory system. The signals may be communicated along signal paths or transmission lines. The memory system may include memory dies that include the storage elements that store data. The memory dies have an associated die capacitance, which in turn affects the characteristic impedances of the transmission lines and the operation frequency or bandwidth at which signals over the transmission lines may be communicated. In general, higher die capacitance limits the frequency or bandwidth at which the signals can be communicated. Accordingly, ways to improve die capacitance to allow for increased frequency and bandwidth without degrading signal quality may be desirable.	2	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The accompanying drawings, which are incorporated in and constitute a part of this specification illustrate various aspects of the invention and together with the description, serve to explain its principles. Wherever convenient, the same reference numbers will be used throughout the drawings to refer to the same or like elements.	3	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1A is a block diagram of an example memory system.	4	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1B is a block diagram of a storage module that includes a plurality of memory systems.	5	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 1C is a block diagram of a hierarchical storage system.	6	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 2A is a block diagram of example components of a controller of the memory system of FIG. 1A.	7	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 2B is a block diagram of example components of a non-volatile memory die of the memory system of FIG. 1A.	8	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 3 is a physical layout of an example configuration of at least some of the components of the controller and a group of dies including an N-number of memory dies and an end die coupled to a transmission line.	9	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 4 is a side view of a plurality of dies integrated as a staircase stack.	10	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 5 is a circuit model of a wire bond portion of the transmission line of FIG. 3.	11	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 6 is an alternative configuration for the group of dies of FIG. 3, where at least one of the N-number of memory dies also include an on-die termination resistance circuit.	12	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Overview	13	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	By way of introduction, the below embodiments relate to reducing effective die capacitance through elimination of on-die termination (ODT) resistance circuits from one or more dies of a die group, such as a die stack, which in turn, may allow for increased frequency, bandwidth, and/or data rates over transmission lines coupled to the die group. In one embodiment, an apparatus that includes a transmission line and a group of dies coupled to the transmission line. The group of dies includes: a first die configured with an on-die termination resistance circuit coupled to the transmission line; and a second die configured without any on-die termination resistance circuits coupled to the transmission line.	14	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, wherein none of the other dies of the group, except the first die, comprises a respective on-die termination resistance circuit coupled to the transmission line.	15	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the first die comprises an end die of the group.	16	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the group of dies is coupled to the transmission line via a wire bond portion of the transmission line.	17	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In some embodiments, the group of dies is configured as a die stack.	18	Added by DJM 12 2021	12/22/21, 12:00 AM

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