Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	FSP1845	The controller die 102 may include a buffer manager/bus controller module 114 that manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration for communication on an internal communications bus 117 of the controller die 102. A read only memory (ROM) 118 may store and/or access system boot code. Although illustrated in FIG. 2A as located separately from the controller die 102, in other embodiments one or both of the RAM 116 and the ROM 118 may be located within the controller die 102. In yet other embodiments, portions of RAM 116 and ROM 118 may be located both within the controller die 102 and outside the controller die 102. Further, in some implementations, the controller die 102, the RAM 116, and the ROM 118 may be located on separate semiconductor dies.	44	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the front end module 108 may include a host interface 120 and a physical layer interface (PHY) 122 that provide the electrical interface with the host or next level storage controller. The choice of the type of the host interface 120 can depend on the type of memory being used. Examples types of the host interface 120 may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 120 may typically facilitate transfer for data, control signals, and timing signals.	45	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The back end module 110 may include an error correction controller (ECC) engine 124 that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the memory dies 104. Additionally, the back end module 110 may include a RAID (Redundant Array of Independent Drives) module 128 that manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the memory system 100. In some cases, the RAID module 128 may be a part of the ECC engine 124.	46	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In addition, the back end module 110 may include a command sequencer 128 and a memory interface 130. The controller die 102 may include a control layer 132 (e.g., a flash controller layer) that controls the overall operation of the back end module 110.	47	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The command sequencer 128 may be configured to generate command sequences, such as program, read, and erase command sequences, to be transmitted to the memory dies 104. The commands of the command sequences that the command sequencer 128 outputs may be referred to as context commands. For example, commands of command sequences for read operations may be referred to as read context commands, and commands of command sequences for write operations may be referred to as write context commands.	48	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory interface 130 is configured to output the command sequences or context commands to the memory dies 104 and receives status information from the memory dies 104. Along with the command sequences and status information, the memory interface 130 may also be configured to send and receive data, such as in the form of data signals, to be programmed into and read from the memory dies 104. The memory interface 130 may also be configured to output clock signals or strobe signals to control the timing at which the memory dies 104 receive data signals carrying data to be programmed and/or at which the memory dies 104 output data signals carrying data the controller die 102 wants read from the memory dies 104.	49	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	As shown in FIG. 2A, the memory system 100 may include a plurality of transmission (Tx) lines (or channels) 134 connecting the controller die 102 and the plurality of memory dies 104. In general, a transmission line is any conductive structure or combination of conductive structures configured to conduct alternating current (AC) or radio frequency (RF) signals from a transmitter that is transmitting the signals to a receiver that is receiving the signals. For the example memory systems described herein, transmission lines are included to communicate signals between (including to and from) the controller die 102 and the memory dies 104. The controller die 102 and the memory dies 104 may be configured to communicate signals--including data signals, clock signals, and command signals--over the plurality of transmission (Tx) lines 134. A signal that is communicated between the controller die 102 and the memory dies 104 may be either transmitted from the controller die 102 over one of the transmission lines 134 to the memory dies 104, or transmitted from the memory dies 104 over one of the transmission lines 134 to the controller die 102. In this context, the controller die 102 and each of the memory dies 104 may be configured as transceiver circuits (or dies) in that they may each be configured to transmit and receive signals.	50	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The controller 102 may be coupled to the transmission lines 134 via its memory interface 130. When the controller die 102 wants to send a signal to the memory dies 104, the controller die 102 may send the signal through its memory interface 130 onto one of the transmission lines 134. The memory dies 104 may each have their own respective memory interfaces to send and receive signals, as described in further detail below with respect to FIG. 3. When referring to the memory interfaces, the memory interface of the controller die 102 may be referred to as a controller-side memory interface 130, and the memory interfaces of the memory dies 104 may be referred to as memory-side memory interfaces.	51	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the memory interface 130 may include or be in communication with controller input/output (I/O) circuitry 136, which includes the circuitry that sends, receives, and generates the analog signals communicated on the transmission lines 134. The controller I/O circuitry 136 may include any of various configurations or circuitry topologies to send, receive, and generate signals. For example, to generate and output signals onto the transmission lines 134, the controller I/O circuitry 136 may include output driver circuits, such as in the form of push-pull circuits, that generate analog signals on the transmission lines 134 at certain predetermined high and low voltage levels. Also, to receive signals from the transmission lines 134, the controller I/O circuitry 136 may include input circuitry, such as in the form of input buffers, which, in some embodiments, may include comparators, such as Schmitt triggers or differential comparators, as non-limiting examples. In various embodiments, the I/O circuitry 136 may include other circuit components, such as pre-driver circuits, level shifter circuits, sampling circuits (e.g., latches or flip flops), and/or multiplexers, to transmit, receive, and generate the signals communicated on the transmission lines. Additionally, the controller I/O circuitry 136 may include conductive components, such as I/O contact pads disposed on the controller die 102 that connect to the transmission lines 134.	52	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additionally, the memory interface 130 and/or the controller I/O circuitry 136 may be configured to communicate with the memory dies 104 over the transmission lines 134 using any of various transmission modes, types, protocols, standards, or formats, non-limiting examples of which include double data rate (DDR), and/or a Toggle Mode (TM), such as TM 200, 400, or 800.	53	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Additional modules of the non-volatile memory system 100 illustrated in FIG. 2A may include a media management layer 138, which may perform certain memory functions, such as address management (e.g., address translation) and wear leveling of memory cells of the memory dies 104. The memory system 100 may also include other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with the controller die 102. In alternative embodiments, one or more of the RAID module 128, media management layer 138 and buffer management/bus controller 114 are optional components that may not be necessary in the controller die 102.	54	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	FIG. 2B is a block diagram illustrating exemplary components of one of the memory dies 104 in more detail. The non-volatile memory die 104 may include a memory cell structure 142. In some example configurations, the memory cell structure 142 may be configured in the form of an array, such as two-dimensional or a three-dimensional array.	55	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Any suitable type of memory can be used for the memory cells 142. As examples, the memory can be dynamic random access memory ("DRAM") or static random access memory ("SRAM"), non-volatile memory, such as resistive random access memory ("ReRAM"), electrically erasable programmable read only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), magnetoresistive random access memory ("MRAM"), phase-change memory ("PCM"), or other elements comprising semiconductor or other material capable of storing information. Each type of memory may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.	56	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.	57	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.	58	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.	59	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.	60	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.	61	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).	62	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	FSP1845	As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in they direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.	63	Added by DJM 12 2021	12/22/21, 12:00 AM

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