Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	US10998041B1	Next, the read scan circuit 1204 may determine a second read level for the second memory state using the correlation. This correlation may be stored in the correlation data structure 1208 (e.g., shift correlation table 900 and/or width correlation table 1000) available in volatile memory 1206. Determining a correlation factor may involve the read scan circuit 1204 searching the correlation data structure 1208 based on an identifier (e.g., `Er`, `A`, `B`, `C`, etc.) for one of two adjacent memory states associated with the read level being scanned/checked. The read scan circuit 1204 may then apply the determined correlation factor to the second read level.	223	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In certain embodiments, a read scan circuit 1204 may apply a correlation factor directly to a current read level for a second memory state and thereby determine the second read level without testing or checking candidate read levels for a second read level window. For example, the read scan circuit 1204 may multiple the current read level by the correlation factor that represents a correlation between the first memory state and the second memory state. In such an embodiment, determining the second read level may be more efficient and may be made possible where the correlation between two memory states is strong enough to skip testing candidate read levels for a second read level window 1104.	224	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	in certain embodiments, read scan operations may be more efficient if a first read level for a first memory state may be determined through thorough scanning, checking, or testing. Next, a correlation, that is as accurate as possible, between the first memory state and second memory state may be used to determine read levels, or adjustments to read levels for the second memory state. Read levels for the second memory state may, in some embodiments, be adjusted based on the correlation, obviating the need for equally thorough (and time consuming) testing for adjustments to read levels associated with the second memory state.	225	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, the read scan circuit 1204 may determine the second read level by multiplying a current read level for the second memory state by a correlation factor representative of the correlation. In other embodiments, the read scan circuit 1204 may determine the second read level by choosing a second set of candidate read levels based on the correlation. This second set of candidate read levels may be smaller than the first set of candidate read levels (e.g., second read level window 1104 as illustrated in FIG. 11 may be smaller than read level window 608 shown in FIG. 6). The read scan circuit 1204 iteratively tests the second set of candidate read levels until the candidate read level activates a fewest number of memory cells in relation to other candidate read levels within the second set of candidate read levels to determine the second read level for the second memory state.	226	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The read scan circuit 1204 may thus be used by the die controller 1202 to determine the most suitable read levels for memory states as described above for the first read level and the second read level. The die controller 1202 may then interact with the state machine 214 and read/write circuits 208 to set the first read level and the second read level, as well as other determined read levels for the memory states expressed by the memory cells of the non-volatile memory array 206. These set read levels may be used for subsequent read operations.	227	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 13 is a schematic block diagram of a storage system 1300 in accordance with one embodiment. The storage system 1300 may include a storage device 1302 that comprises a storage controller 1304 and non-volatile memory array 206. The storage controller 1304 may further comprise a read/write circuit 1306, an error correction code decoder 1308, and a health manager 1310 including a read scan circuit 1312. Those of skill in the art will appreciate that these components may be incorporated within other parts of the storage device 1302 or may be carried out by the host 106 in certain embodiments.	228	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Health manager" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to review, test, check, configure, adjust, and/or adapt configuration parameters for memory cells, a memory die, and/or a storage controller so as to prolong the usefulness, effectiveness, and/or efficiency of a storage device.	229	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The read/write circuit 1306 is configured to service storage operations to provide storage services to one or more storage clients 110. The read/write circuit 1306 may be configured to write data to memory cells of the plurality of memory dies 104. The read/write circuit 1306 coordinates with the error correction code decoder 1308 to service write commands and read commands.	230	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The health manager 1310, in one embodiment, may manage and monitor the health of the non-volatile storage media of the non-volatile memory array 206. In one embodiment, the health manager 1310 executes a read scan operation on one or more, or each of the storage blocks of the non-volatile memory array 206. As the health manager 1310 detects storage blocks having a health condition that is causing more bit errors (a higher bit error rate), the health manager 1310 may adjust read levels for memory states to reduce a bit error rate, recover data, and/or extend the life of non-volatile storage media.	231	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The health manager 1310 may include a read scan circuit 1312 and a calibration circuit 1314. "Read scan circuit" refers to any circuit, sub-circuit, electronic component, hardware, software, firmware, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to execute a read scan operation. "Calibration circuit" refers to any circuit, sub-circuit, electronic component, hardware, software, firmware, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to change, alter, modify, update, configure, or calibrate a configuration parameter, including but not limited to a read level.	232	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The read scan circuit 1312 reads data from storage blocks of the non-volatile memory array 206 and coordinates with the health manager 1310 to determine a health for the storage cells of the storage block. The read scan circuit 1312 may implement a read scan operation and may check memory state read levels of each storage block.	233	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The read scan circuit 1312 may read data from a storage block to determine appropriate read levels. For example, in one embodiment, the health manager 1310 may implement a BES read scan operation using the read scan circuit 1312, calibration circuit 1314, and error correction code decoder 1308. The read scan circuit 1312 may coordinate with the error correction code decoder 1308 to determine a bit error rate, or an estimated or proxy bit error rate, for each read of a storage block, this bit error rate may be called a read bit error rate. In one embodiment, the error correction code decoder 1308 determines the bit error rate without doing any error correction or detection. In another embodiment, the error correction code decoder 1308 determines the bit error rate after attempting or completing error correction or detection.	234	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Error correction code decoder" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to detect and/or correct errors in a data set using redundancy information defined for the data set (e.g., a code word). The error correction code decoder, in one embodiment, may comprise one or more types of decoder, including, but not limited to, a low density parity check (LDPC) decoder, a Reed-Solomon code decoder, a Golay code decoder, a Bose Chaudhuri Hocquenghem (BCH) code decoder, a turbo code decoder, a multidimensional parity code decoder, a Hamming code decoder, a Hadamard code decoder, an expander code decoder, a Reed-Muller code decoder, a Viterbi decoder, a Fano decoder, or the like.	235	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, the read scan circuit 1312 manages the non-volatile memory array 206 by proactively setting and adjusting configuration parameters for storage cells of the non-volatile memory array 206. By determining configuration parameters proactively before an error occurs, the read scan circuit 1312 may prevent certain errors from occurring, without the performance penalty of retrying reads or performing other remedial measures for the prevented errors. The read scan circuit 1312, in certain embodiments, adapts configuration parameters for a use case of the storage device 1302 to configure storage cells for the use case instead of using default configuration parameters.	236	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The read scan circuit 1312 references one or more media characteristics for a set of storage cells to determine a configuration parameter for the set of storage cells. The read scan circuit 1312, in response to determining a configuration parameter for a set of storage cells, may configure the set of storage cells to use the determined configuration parameter. The read scan circuit 1312 may periodically update media characteristics for a set of storage cells, update a configuration parameter for the set of storage cells, and reconfigure the set of storage cells to use the updated configuration parameter. The read scan circuit 1312 may configure storage cells with configuration parameters during execution of input/output operations, during a startup operation, in response to a background scan of a set of storage cells indicating a changed media characteristic, or the like.	237	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, the health manager 1310 may implement a BES read scan operation that uses the read scan circuit 1312. The read scan circuit 1312 may iteratively read data of a storage block using a predetermined number of candidate read levels. The read scan circuit 1312 may test candidate read levels of a set of candidate read levels based on a correlation between two memory states for memory cells of the storage block. The error correction code decoder 1308 may determine an estimated bit error rate for the data read during the read scan operation (e.g., as part of a BES read scan operation), and the calibration circuit 1314 may calibrate memory cells based on the read levels determined by the read scan circuit 1312.	238	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, the read scan circuit 1312 may determine a first read level for reading data programmed to a first set of memory cells of the storage block 1316. The first set of memory cells may be associated with a first memory state.	239	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The read scan circuit 1312 may determine a correlation between a memory state for the first set of memory cells and a memory state for a second set of memory cells. Next, the read scan circuit 1312 may determine a second read level for reading data programmed to the second set of memory cells. The second read level may be determined based on the correlation between the memory state for the first set of memory cells and the memory state for the second set of memory cells.	240	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The read scan circuit 1312 may then set the first read level as a current read level for reading data from the first set of memory cells and may set the second read level as a current read level for reading data from the second set of memory cells. One skilled in the art will recognize that the read scan circuit 1312 and calibration circuit 1314 may reside in logic modules other than a health manager 1310. This illustration is not intended to limit this aspect of the disclosed system.	241	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 14 illustrates a method for conducting a read scan operation 1400 in accordance with one embodiment. At block 1402, a read scan circuit may scan a first read level window for a first candidate read level that activates the fewest number of memory cells in relation to other candidate read levels within the first read level window. The first read level window may test read levels between two adjacent memory states.	242	Added by DJM 12 2021	12/22/21, 12:00 AM

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