Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	US10998041B1	"Threshold voltage" refers to a voltage level that when applied to a gate terminal of a transistor causes the transistor to conduct a current between the drain electrode and source electrode.	75	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Consequently, a non-volatile memory array is a memory array having memory cells configured such that a characteristic (e.g., threshold voltage level, resistance level, conductivity, etc.) of the memory cell used to represent stored data remains a property of the memory cell without a requirement for using a power source to maintain the characteristic.	76	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A memory array is addressable using a row identifier and a column identifier. Those of skill in the art recognize that a memory array may comprise the set of memory cells within a plane, the set of memory cells within a memory die, the set of memory cells within a set of planes, the set of memory cells within a set of memory die, the set of memory cells within a memory package, the set of memory cells within a set of memory packages, or with other known memory cell set architectures and configurations.	77	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A memory array may include a set of memory cells at a number of levels of organization within a storage or memory system. In one embodiment, memory cells within a plane may be organized into a memory array. In one embodiment, memory cells within a plurality of planes of a memory die may be organized into a memory array. In one embodiment, memory cells within a plurality of memory dies of a memory device may be organized into a memory array. In one embodiment, memory cells within a plurality of memory devices of a storage system may be organized into a memory array.	78	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The non-volatile memory array 206 is addressable by word line via a row decoder 210 and by bit line via a column decoder 212. "Word line" refers to a structure within a memory array comprising a set of memory cells. The memory array is configured such that the operational memory cells of the word line are read or sensed during a read operation. Similarly, the memory array is configured such that the operational memory cells of the word line are read, or sensed, during a read operation. A word line may also be referred to as a physical page or page for short. "Bit line" refers to a circuit structure configured to deliver a voltage and/or conduct current to a column of a memory array. In one embodiment, the column comprises a NAND string or memory string and may also be referred to as channel. In one embodiment, the column is referred to as a NAND string and the NAND string comprises a channel. In one embodiment, a bit line connects to a NAND string at a drain end or drain side of the NAND string. A memory array may have one bit line for each memory cell along the word lines of the memory array.	79	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Channel" refers to a structure within a memory array that extends from a source side to a drain side. In one embodiment, a channel is a vertical column within a memory array that forms a conductive path between a source line coupled to one end of a NAND string and a bit line coupled to another end of the NAND string. A channel may be formed from a variety of materials including, for example, polysilicon.	80	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, a channel within a NAND string creates a conductive path by activating one or more memory cells (e.g., one or more selected memory cells and unselected memory cells) along the NAND string, and one or more control structures (e.g., select gates (source and/or drain) between a source line connected to one end (e.g., the source side) of the NAND string and a sense amplifier or bit line connected to the other end (e.g., the drain side) of the NAND string.	81	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Select gate" refers to a transistor structurally and/or electrically configured to function as a switch to electrically connect a first electrical structure connected to a source terminal of the transistor to a second electrical structure connected to the drain terminal. When functioning as a switch, the transistor is referred to herein as a `select gate` and serves to gate (selectively) or control when, and in what quantity, a current flows or a voltage passes between the first electrical structure and the second electrical structure. Depending on the context, references to select gate herein may refer to the whole transistor or to the gate terminal of the transistor.	82	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The read/write circuits 208 include multiple sense blocks SB1, SB2, . . . , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. In certain embodiments, each memory cell across a row of the memory array together form a physical page. "Read/write circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured and/or operational to read data from and write data to a storage media, such as storage cells of a storage array.	83	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A physical page may include memory cells along a row of the memory array for a single plane or for a single memory die. In one embodiment, the memory die includes a memory array made up of two equal sized planes. In one embodiment, a physical page of one plane of a memory die includes four data blocks (e.g., 16 KB). In one embodiment, a physical page (also called a "die page") of a memory die includes two planes each having four data blocks (e.g., 32 KB).	84	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Commands and data are transferred between the host 106 and storage controller 102 via a data bus 112, and between the storage controller 102 and the one or more memory dies 104 via bus 114. The storage controller 102 may comprise the logical modules described in more detail with respect to FIG. 1.	85	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The non-volatile memory array 206 can be two-dimensional (2D--laid out in a single fabrication plane) or three-dimensional (3D--laid out in multiple fabrication planes). The non-volatile memory array 206 may comprise one or more arrays of memory cells including a 3D array. In one embodiment, the non-volatile memory array 206 may comprise a monolithic three-dimensional memory structure (3D array) in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The non-volatile memory array 206 may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The non-volatile memory array 206 may be in a non-volatile solid-state drive having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.	86	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Word lines may comprise sections of the layers containing memory cells, disposed in layers above the substrate. Multiple word lines may be formed on single layer by means of trenches or other non-conductive isolating features.	87	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The die controller 204 cooperates with the read/write circuits 208 to perform memory operations on memory cells of the non-volatile memory array 206, and includes a state machine 214, an address decoder 216, and a power control 218. The state machine 214 provides chip-level control of memory operations. "Die controller" refers to a set of circuits, circuitry, logic, or components configured to manage the operation of a die. In one embodiment, the die controller is an integrated circuit. In another embodiment, the die controller is a combination of discrete components. In another embodiment, the die controller is a combination of one or more integrated circuits and one or more discrete components.	88	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The address decoder 216 provides an address interface between that used by the host or a storage controller 102 to the hardware address used by the row decoder 210 and column decoder 212. The power control 218 controls the power and voltages supplied to the various control lines during memory operations. "Control line" refers to a structure, circuit, circuitry, and/or associated logic configured to convey an electrical current and/or voltage from a source to a destination. In certain embodiments, analog voltages, currents, biases, and/or digital signals supplied or discharged over a control line are used to control switches, select gates, and/or other electrical components. Certain control lines may have a specific name based on what parts of a circuit the control line controls or where the control line couples, or connects, to other circuits. Examples of named control lines include word lines, bit lines, source control lines, drain control lines, and the like.	89	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Source control line" refers to a control line configured to operate a select gate (e.g., turn the select gate on, activate, and off, deactivate) for coupling a source side of a NAND string to a source line and/or another circuit.	90	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Source side" refers to the end of a NAND string or side of a three-dimensional memory array connected to the source layer or line on a memory die. The term comes from the source terminal of a field effect transistor or similar component. In a daisy-chained string of transistors, the source terminal of the first transistor may be connected to a source line, a ground or some other lower voltage line, and the drain terminal may be connected to the source terminal of the next transistor, that transistor's drain terminal may be connected to the next source terminal and so on, with the drain terminal of the final transistor connected to a higher voltage signal or power line. The gate terminal of each transistor may then control whether or not current flows through the transistor from source to drain, and through the string from source line to bit line.	91	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Source line" refers to a structure, circuit, circuitry, and/or associated logic configured to convey an electrical current and/or voltage from a supply to one or more channels of associated NAND strings. In certain embodiments, a source line is configured to convey a voltage to, and/or discharge a voltage from multiple NAND strings concurrently. In other embodiments, a source line is configured to convey a voltage to, and/or discharge a voltage from multiple NAND strings in series.	92	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In certain embodiments, a source control line couples to one or more source-side select gates that are between the source line and one or more NAND strings and the source control line manages whether voltage or current passes between the source line and the NAND string. In such an embodiment, the source line may also be referred to as a common source line.	93	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Source-side select gate" refers to a select gate functioning as a switch to electrically connect a source line to a NAND string and/or a channel of a NAND string. Examples of source lines include source-side select gates, dummy word line select gates, and the like. In certain embodiments, a source-side select gate may comprise just source-side select gates (e.g., SGS0, SGS1, etc.). In other embodiments, a source-side select gate may comprise just dummy word line select gates (e.g., DWLS0, DWLS1, etc.). In still other embodiments, a source-side select gate may comprise both source-side select gates (e.g., SGS0, SGS1, etc.) and dummy word line select gates (e.g., DWLS0, DWLS1, etc.). A select gate positioned between the source line and the NAND string on the source side of the NAND string is referred to as a source-side select gate.	94	Added by DJM 12 2021	12/22/21, 12:00 AM

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