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"Drain control line" refers to a control line configured to operate a select gate (e.g., turn the select gate on, activate, and off, deactivate) for coupling a drain side of a NAND string to a bit line and/or a sense circuit. "Drain side" refers to the end of a NAND string or side of a three-dimensional memory array connected to the bit line(s). The term comes from the drain terminal of a field effect transistor or similar component. In a daisy-chained string of transistors, the source terminal of the first transistor may be connected to a source line, a ground or some other lower voltage line, and the drain terminal may be connected to the source terminal of the next transistor, that transistor's drain terminal may be connected to the next source terminal and so on, with the drain terminal of the final transistor connected to a higher voltage signal or power line. The gate terminal of each transistor may then control whether or not current flows through the transistor from source to drain, and through the string from source line to bit line. |
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"Drain-side select gate" refers to a select gate functioning as a switch to electrically connect a bit line to a NAND string and/or a channel of a NAND string. A select gate positioned between the bit line and the NAND string on the drain side of the NAND string is referred to as a drain-side select gate. |
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"Logic" refers to machine memory circuits, non-transitory machine readable media, and/or circuitry which by way of its material and/or material-energy configuration comprises control and/or procedural signals, and/or settings and values (such as resistance, impedance, capacitance, inductance, current/voltage ratings, etc.), that may be applied to influence the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and nonvolatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (however does not exclude machine memories comprising software and thereby forming configurations of matter). |
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The power control 218 and/or read/write circuits 208 can include drivers for word lines, source gate select (SGS) transistors, drain gate select (DGS) transistors, bit lines, substrates (in 2D memory structures), charge pumps, and source lines. In certain embodiments, the power control 218 may detect a sudden loss of power and take precautionary actions. The power control 218 may include various first voltage generators (e.g., the drivers) to generate the voltages described herein. The sense blocks can include bit line drivers and sense amplifiers in one approach. |
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In some implementations, some of the components can be combined. In various designs, one or more of the components (alone or in combination), other than non-volatile memory array 206, can be thought of as at least one control circuit or storage controller which is configured to perform the techniques described herein. For example, a control circuit may include any one of, or a combination of, die controller 204, state machine 214, address decoder 216, column decoder 212, power control 218, sense blocks SB1, SB2, SBp, read/write circuits 208, storage controller 102, and so forth. |
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In one embodiment, the host 106 is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor readable storage devices (RAM, ROM, FLASH memory, hard disk drive, solid state memory) that store processor readable code (e.g., software) for programming the storage controller 102 to perform the methods described herein. The host may also include additional system memory, one or more input/output interfaces and/or one or more input/output devices in communication with the one or more processors, as well as other components well known in the art. |
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Associated circuitry is typically involved in operation of the memory cells and for communication with the memory cells. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory cells to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory cells and/or on a separate substrate. For example, a storage controller for memory read-write operations may be located on a separate storage controller chip and/or on the same substrate as the memory cells. |
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One of skill in the art will recognize that the disclosed techniques and devices are not limited to the two-dimensional and three-dimensional exemplary structures described but covers all relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of skill in the art. |
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FIG. 3 illustrates a memory array 300 in accordance with one embodiment. In the illustrated embodiment, memory array 300 is organized into logical erase blocks (LEBs), as shown by logical erase block 302 (also referred to herein as a "metablock" or "superblock"). These LEBs include multiple physical erase blocks (PEBs) illustrated by physical erase block 0 304, physical erase block n 306, physical erase block 0 308, physical erase block n 310, physical erase block 0 312, and physical erase block n 314. "Physical erase block" refers to smallest storage unit within a given memory die that can be erased at a given time (e.g., due to the wiring of storage cells on the memory die). |
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The physical erase blocks may be located in separate storage dies, shown as die 0 316, die 1 318, and die n 320. In certain embodiments, a die is divided into planes. "Plane" refers to a division of a die that permits certain storage operations to be performed on both planes using certain physical row addresses and certain physical column addresses. |
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"Storage block" refers to a set of storage cells organized such that storage operations can be performed on groups of storage cells in parallel. The organization of the set of storage cells may be implemented at a physical level or a logical level. Thus, a storage block, in one embodiment, may comprise a physical page, such as a word line, a logical page comprising physical pages that span planes and/or memory die, a physical erase block comprising a set of physical pages, a logical erase block (LEB) comprising a set of logical pages, or the like. A storage block may be referred to herein as a "block", a "memory block" or an LEB. |
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"Logical erase block" refers to another term for a storage block. In certain embodiments, a logical erase block refers to a set of logical pages that span planes, memory die, and/or chips. This organization of storage cells is deemed `logical` because the physical pages may not be directly coupled to each other. However, the physical pages are operated in parallel as though they are a single page. In like manner, multiple physical erase blocks may be operated in parallel as though they are a single erase block and are thus referred to as logical erase blocks. The terms logical erase block, metablock, and super block are used interchangeably herein. |
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"Logical page" refers to a collection of physical page that are treated as a single page for storage operations. "Physical page" refers to physical page represents the smallest storage block within a given memory die that can be written to in a single operation. |
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A logical erase block such as logical erase block 302 is further divided into multiple logical pages (logical page 322) that, in turn, includes multiple physical pages, such as physical page 0 324, physical page n 326, physical page 0 328, physical page n 330, physical page 0 332, and physical page n 334. Physical pages may include multiple packets, which may be grouped into error correction code (ECC) chunks. |
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In one embodiment, a physical page represents the smallest storage block within a given die that can be written to at a given time. In one embodiment, a logical page is the smallest writable storage block supported by the storage controller. (in one embodiment, the storage controller may include a buffer configured to store up to a logical page worth of data; upon filling the buffer, the storage controller may write the contents of the buffer to a single logical page simultaneously.) In some instances, dividing a logical page across multiple dies may result in faster access times for a set of data when multiple dies are accessed in parallel. The logical page configurations may be mapped to any physical page on a die, or across a plurality of memory dies, just as with logical erase blocks. |
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In some embodiments, a storage controller 102 may associate metadata, also referred to as media characteristics, with one or more of the storage blocks (logical erase blocks, physical erase blocks, logical pages, and/or physical pages). The storage controller 102 may manage metadata that identifies logical addresses for which a logical erase block stores data, as well as the respective numbers of stored data packets for each logical erase block, data block, or sector within a logical address space. A storage controller 102 may store metadata or media characteristic data in a variety of locations, including on non-volatile storage media, in volatile memory, in a structure stored with each logical erase block, or the like. |
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"Media characteristic" refers to an attribute or statistic for a set of particular storage cells, such as a program/erase cycle count for the set of storage cells, a read count for the set of storage cells, a retention time since a previous write for the set of storage cells (aka a data retention time), a dwell time for the set of storage cells such as a logical or physical erase block (e.g., a time between a program of an erase block and an erase of the erase block), an average of multiple previous dwell times for the set of storage cells, an error statistic for the set of storage cells, or the like. |
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A media characteristic for a set of storage cells may be substantially static or may be dynamic and change over time. A media characteristic, in one embodiment, is a statistic, heuristic, mathematical model, transform, or other descriptor associated with an attribute of the non-volatile memory media. |
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A media characteristic, in one embodiment, includes or relates to a make, a model, a manufacturer, a product version, or the like for the storage device and/or for the non-volatile memory media. A media characteristic, in a further embodiment, may include or relate to an environmental condition or a use of the storage device and/or of the non-volatile memory media, such as a temperature, a use case (e.g., a cache use case, an archival use case, a server use case, an enterprise use case, a consumer use case, etc.), or the like. |
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FIG. 4 shows a graph of a cell threshold voltage distribution for memory cells of a non-volatile storage media and cell threshold voltage distribution curves 400 such as multi-level NAND flash storage cells, or the like. The memory states, in the depicted embodiment, may be encoded using a gray code encoding model, with binary values for adjacent memory states differing by a single bit in the encoding. |
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