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US6559866B2
In response to an interactive option becoming available, an icon sharing visual characteristics with a corresponding button of a remote control is displayed. A description of the interactive option in the language of the user may also be presented visually or audibly. The icon and description may be displayed alone or in a configuration of a map of the remote control. The description may be audibly output using voice synthesis techniques.
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US10998041B1
The computing device 1500 may include logic that enables communications over a network using protocols such as HTTP, TCP/IP, RTP/RTSP, IPX, UDP and the like.
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US10998041B1
The volatile memory 1518 and the non-volatile memory 1520 are examples of tangible media configured to store computer readable data and instructions to implement various embodiments of the processes described herein. Other types of tangible media include removable memory (e.g., pluggable USB memory devices, mobile device SIM cards), optical storage media such as CD-ROMS, DVDs, semiconductor memories such as flash memories, non-transitory read-only-memories (ROMS), battery-backed volatile memories, networked storage devices, and the like. The volatile memory 1518 and the non-volatile memory 1520 may be configured to store the basic programming and data constructs that provide the functionality of the disclosed processes and other embodiments thereof that fall within the scope of the present disclosure.
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US10998041B1
Logic 1522 that implements one or more parts of embodiments of the solution may be stored in the volatile memory 1518 and/or the non-volatile memory 1520. Logic 1522 may be read from the volatile memory 1518 and/or non-volatile memory 1520 and executed by the processor(s) 1512. The volatile memory 1518 and the non-volatile memory 1520 may also provide a repository for storing data used by the logic 1522. "Repository" refers to any data source or dataset that includes data, or content. In one embodiment, a repository resides on a computing device. In another embodiment, a repository resides on a remote computing or remote storage device. A repository may comprise a file, a folder, a directory, a set of files, a set of folders, a set of directories, a database, an application, a software application, content of a text, content of an email, content of a calendar entry, and the like. A repository, in one embodiment, comprises unstructured data. A repository, in one embodiment, comprises structured data such as a table, an array, a queue, a look up table, a hash table, a heap, a stack, or the like. A repository may store data in any format including binary, text, encrypted, unencrypted, a proprietary format, or the like.
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US10998041B1
The volatile memory 1518 and the non-volatile memory 1520 may include a number of memories including a main random access memory (RAM) for storage of instructions and data during program execution and a read only memory (ROM) in which read-only non-transitory instructions are stored. The volatile memory 1518 and the non-volatile memory 1520 may include a file storage subsystem providing persistent (non-volatile) storage for program and data files. The volatile memory 1518 and the non-volatile memory 1520 may include removable storage systems, such as removable FLASH memory.
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US10998041B1
The bus subsystem 1516 provides a mechanism for enabling the various components and subsystems of data processing system 1502 communicate with each other as intended. Although the communication network interface 1506 is depicted schematically as a single bus, some embodiments of the bus subsystem 1516 may utilize multiple distinct busses.
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US10998041B1
It will be readily apparent to one of ordinary skill in the art that the computing device 1500 may be a device such as a smartphone, a desktop computer, a laptop computer, a rack-mounted computer system, a computer server, or a tablet computer device. As commonly known in the art, the computing device 1500 may be implemented as a collection of multiple networked computing devices. Further, the computing device 1500 will typically include operating system logic (not illustrated) the types and nature of which are well known in the art.
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US10998041B1
Terms used herein should be accorded their ordinary meaning in the relevant arts, or the meaning indicated by their use in context, but if an express definition is provided, that meaning controls.
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US10998041B1
Within this disclosure, different entities (which may variously be referred to as "units," "circuits," other components, etc.) may be described or claimed as "configured" to perform one or more tasks or operations. This formulation--[entity] configured to [perform one or more tasks]--is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be "configured to" perform some task even if the structure is not currently being operated. A "credit distribution circuit configured to distribute credits to a plurality of processor cores" is intended to cover, for example, an integrated circuit that has circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as "configured to" perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.
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US10998041B1
The term "configured to" is not intended to mean "configurable to." An unprogrammed FPGA, for example, would not be considered to be "configured to" perform some specific function, although it may be "configurable to" perform that function after programming.
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US10998041B1
As used herein, the term "based on" is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase "determine A based on B." This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."
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US10998041B1
As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase "perform A in response to B." This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.
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US10998041B1
As used herein, the terms "first," "second," etc., are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. For example, in a register file having eight registers, the terms "first register" and "second register" can be used to refer to any two of the eight registers, and not, for example, just logical registers 0 and 1.
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US10998041B1
"Read level window" refers to a set of candidate read levels that may serve as a read level between two adjacent memory states. In certain embodiments, where the memory cells that are read a read using one or more threshold voltages, a read level window may comprise a set of threshold voltages between a low threshold voltage and a high threshold voltage, with each member of the set of candidate read levels within the read level window comprising a distinct threshold voltage.
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US10998041B1
In another embodiment comprise NAND memory cells, a read level window may comprise a set of threshold voltages between a low threshold voltage and a high threshold voltage, with each member of the set of candidate read levels within the read level window comprising a threshold voltage offset by one or more offset amounts from a default read level, such as a current read level. The offsets from the default read level may be both greater than and/or less than the default read level. A read level window may also be referred to as a "scanning" window.
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US10998041B1
FIG. 6 includes read level window 602, read level window 604, read level window 606, and read level window 608, one for each read level A 406, read level D 412, read level F 416, and read level K 426, respectively. For each read level window, scanning window, a set of sets of candidate read levels 610 may be used. For example, threshold voltage levels #1-#7 may be the candidate read levels used across read level window 602 to determine an optimal placement for read level A 406, levels #8-14 for read level D 1110, levels #15-21 for read level F 416, and levels #22-28 for read level K 1114.
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US10998041B1
By way of example, a valley search operation may iteratively determine an optimal read level for each of read level A 406, read level D 412, read level F 416, and read level K 426. For read level A 406, suppose the default read level is candidate read level #5 and memory state Er has moved up, shifted to the right and memory state A has shifted to the left, moved down. After determining how many memory cells candidate read level #5 activates (or alternatively how many bit errors are in a code word when read level A 406 is a candidate read level #5), the valley search operation may next check a next highest candidate read level #6 or check a next lowest candidate read level #4.
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US10998041B1
With each iterative check, the valley search operation compares a result (e.g., number of activated memory cells or bit error rate) with a prior result for a previous check. If the candidate read level being checked/tested results in higher bit errors or more activated memory cells, the valley search operation may check a threshold voltage in an opposite direction than the direction that lead to the higher bit errors (activated memory cells). So, if the candidate read level #5 results in fewer activated memory cells than candidate read level #6, then the valley search operation may next test candidate read level #4. If the candidate read level #4 results in fewer activated memory cells than candidate read level #5, then the valley search operation may next test candidate read level #3. If the candidate read level #3 results in more activated memory cells than candidate read level #4, then the valley search operation may stop iterating and determine that candidate read level #4 is the "valley" between the Er memory state and A memory state. Consequently, the valley search operation may change a default read level from candidate read level #5 to candidate read level #4. Next, the valley search operation may follow this similar process for read level D 412, read level F 416, and read level K 426. For example, candidate read levels from read level window 604, read level window 606, and read level window 608 may be iteratively tested. Furthermore, of a valley search operation is done for all logical pages, eventually, all the read levels of the Vt window will be tested and potentially changed to obtain optimal read operation results. A valley search operation is an iterative trial and error method for determining how to adjust read levels.
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US10998041B1
The candidate read levels, for example of read level window 602, may be predefined. In another example, the valley search operation derives the candidate read levels by applying an offset for a last candidate read level.
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US10998041B1
Bit Error Rate Estimation (BES)
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