Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
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View Edit Delete	US10998041B1	"Memory state" refers to a condition, attribute, and/or characteristic, of a memory cell, or storage cell, designed and/or configured to represent an encoding for one or more data bit values. In certain embodiments, the memory state may be changed by way of a storage operation. In a non-volatile memory cell, the memory cell maintains its memory state without a power source.	115	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In certain embodiments, and in certain contexts, memory state may also refer to a collection, or set of memory cells, that collectively have a similar condition, attribute, and/or characteristic. In relation to non-volatile memory cells, groups, collections, or sets of memory cells with a similar condition within a certain range may be referred to collectively as memory cells of a particular memory state. Furthermore, reference may be made to a memory state as a shorthand reference to all memory cells having a condition that falls within a predefined range defined for that memory state.	116	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	For example, with NAND memory cells, a threshold voltage (Vt) window may be defined between a negative threshold voltage, or approximately zero threshold voltage, and a maximum threshold voltage. Within this Vt window, a number of sub-ranges may be defined and referred to as memory states. In certain embodiments, the whole Vt window may be divided up such that each threshold voltage falls within one of the memory states. In one embodiment, each memory state has a lower boundary and an upper boundary and may be represented by a cell threshold voltage distribution.	117	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In FIG. 4, the Vt window may begin at the low end of the erased memory state 402 ("Er") and extend to the upper end/boundary of the "O" memory state. The graph includes erased memory state 402 and memory states "A"-"O" for a total of 16 memory states to represent 4 bits stored in each memory cell. Certain memory states are adjacent memory states. "Adjacent memory state" refers to a memory state that neighbors a given memory state along a range of threshold voltages with no memory states defined between the given memory state and the adjacent memory state. "Er" memory state (erased memory state 402) and "A" memory state are adjacent memory states. Similarly, "A" memory state and "B" memory state are adjacent memory states. "A" memory state and "C" memory state are not adjacent memory states because "B" memory state is between them.	118	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The graph illustrates a threshold voltage for memory cells of a non-volatile storage media along the x-axis. The y-axis identifies a number, or count, of memory cells sensed/detected/read that have the corresponding threshold voltage along the x-axis. The curves within each memory state represent a normal distribution of memory cells that fall within a given memory state. Taken together the curves of the graph illustrate a cell threshold voltage distribution. In certain embodiments, a curve representing memory cells within a particular memory state may also be referred to as a cell threshold voltage distribution. Thus, a cell threshold voltage distribution for non-volatile storage media may include a number of cell threshold voltage distributions.	119	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Cell threshold voltage distribution" refers to a process or method for determining a threshold voltage for each memory cell in a set of memory cells. Cell threshold voltage distribution may be referred to as cell voltage distribution and may be referred to using the acronym "CVD."	120	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A cell threshold voltage distribution may be determined during research and development of non-volatile memory technology to understand how memory cells behave under different conditions. In certain embodiments, a cell threshold voltage distribution may be performed during operation of non-volatile memory to determine whether the read levels being used to read a memory cell are adequate. If a bit error rate for a first set of read levels is inadequate, countermeasures may be taken to reduce the bit error rate.	121	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In certain embodiment, these countermeasures may include adjusting configuration parameters such that a bit error rate decreases. In certain embodiments, the steps of determining a cell threshold voltage distribution, checking read levels and other media characteristics with respect to bit error rate, and taking any countermeasures, may be referred to as a CVD scan, a read scan, or a read scan operation. A CVD scan may require significant time to complete due to the various steps involved and the number of memory cells being scanned. In particular, where memory cells store four or more bits per memory cell, a CVD scan may incur high latency, unless aspects of the claimed solution are used. "Bit error rate" refers to a measure of a number of bits in error of a total overall number of bits processed. Depending on the use case, a bit error rate may be calculated either before, or after, an Error Correction Code (ECC) decoder has made one or more attempts to correct one or more bits in error.	122	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Configuration parameter" refers to a parameter of a set of storage cells that is modifiable by way of an interface, such as a read threshold, a write or program threshold, an erase threshold, or the like. An interface for modifying a configuration parameter may include a programmable data register, a command interface of a control bus for the non-volatile memory array, an API of a device driver of the storage device, a control parameter for the storage controller, or the like.	123	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The threshold voltage for each memory cell may be encoded to represent binary data. In particular, the threshold voltage for each memory cell may be encoded to represent a 2, 3, 4 or more bits per memory cell. For example in FIG. 4, the binary value "1111" may in one embodiment be associated with the lowest memory state (labeled Er, an erased memory state 402), the value "1110" associated with the next lowest read voltage state and first of the QLC programmed memory states 404 (labeled A), the value "1010" associated with the next highest read voltage state (labeled B), and the value "1000" associated with the next highest read voltage state (labeled C), and so on, with only one bit changing between memory states, also referred to as read voltage states.	124	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In FIG. 4, the lowest memory state Er is depicted as a negative threshold voltage below the depicted 0.0V. In other embodiments, the lowest memory state Er may comprise a positive threshold voltage above the 0.0V level, or span the 0.0V level. Values, magnitudes, sizes, and the like of read voltages may vary by manufacturer and type of non-volatile memory cell, each of which are encompassed by this disclosure. A read level is used by the die controller to distinguish memory cells in one memory state from those in another.	125	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Read level" refers to a voltage level configured to test, check, read, or sense, which memory cells conduct at the voltage level. In certain embodiments, the memory cells may comprise transistors and the read level, or read voltage, is a voltage level at, or above a threshold voltage for the memory cells which causes the memory cell to conduct a current, to activate.	126	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In certain embodiments, depending on the type of encoding used to store data on the memory cell and the number of bits encoded on each memory cell, a single read/sense operation using a single read voltage may be determinative of the memory state of the memory cell. In other embodiments, a number of read/sense operations each performed at different read voltage levels may be used to determine the memory state of the memory cell.	127	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The determined memory state may then be decoded into a representation of the data bits stored by the memory cell. "Read voltage" is a shorthand reference to a "read threshold voltage." "Read level" is another term commonly used to describe a "read voltage" and the two terms are used interchangeably herein. Reading memory cells based on a read level may be used for reading stored data in the memory cells as well as testing/checking performance of the memory cells and determining whether to make any changes to configuration parameters for the memory cells.	128	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 4 illustrates multiple default read levels which may be set at the time a storage device 200 is manufactured and may be tuned during a manufacturing process and/or later when the storage device 200 is in use by a customer. When memory cells are programmed, the threshold voltages are changed from the erased memory state 402 to one of the QLC programmed memory states 404. Each memory state is bounded by a default read level. If a programmed, operational, memory cell does not activate at a default read level, the threshold voltage of the memory cell is above the default read level. The read or sense storage operation is an iterative process. And completing the iterative process, either for reading data or for sensing all memory cells, such as with CVD, identifies each memory cell as a member of one of the erased memory state 402 or QLC programmed memory states 404.	129	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Read level A 406, read level B 408, read level C 410, read level D 412, read level E 414, read level F 416, read level G 418, read level H 420, read level I 422, read level J 424, read level K 426, read level L 428, read level M 430, read level N 432, and read level O 434 in the depicted embodiment, may comprise default read levels that separate memory states A from Er, B from A, C from B, etc., respectively. While default read levels may be set at the time of manufacture, they may be adjusted, as needed to ensure optimal performance of the memory cells. In certain embodiments, a default read level represents a current read level for a memory cell. "Current read level" refers to a read level that is a value that is presently being used by a die controller or storage controller for read operations on memory cells. In certain embodiments, a current read level may be a default read level that has been used for prior read operations. In another embodiment, the current read level may comprise a read level set by a prior read scan operation and which may be changed in a presently executing read scan operation.	130	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A program storage operation changes a media characteristic, e.g., threshold voltage, of the memory cells to a different state to represent a programmed condition. By setting the media characteristic to one of a plurality of different states according to a particular encoding, multiple bits may be stored in a single memory cell. With NAND memory cells, the program operation changes the threshold voltage to a threshold voltage between two read levels. For example, in one embodiment, a program operation may program certain memory cells to an H memory state by changing the threshold voltage to a level between read level H 420 and read level I 422. In certain embodiments, additional thresholds may be used, including a programming level, a program verify level, and the like.	131	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Based on a data encoding, a non-volatile memory storage controller may interpret discrete threshold voltages for a quad-level storage cell as representing four binary bits. FIG. 4 and FIG. 5 illustrate an embodiment that uses a Gray code encoding. Other programming and encoding models may be used, and certain non-volatile memory media may have more or fewer possible states, allowing other amounts of data to be stored in a single storage cell. The memory states A through O may or may not be contiguous; for example, in certain embodiments, the voltage levels may be separated by band gaps known as guard bands. For example, A and B may be separated by 0.3V. The memory states A through O may alternately exhibit overlap as illustrated in FIG. 6.	132	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Referring now to FIG. 4 and FIG. 5, FIG. 4 illustrates cell threshold voltage distribution curves 400. The illustrated voltage distribution curves are for memory cells programmed to store four bits of data. At a given point in time, each memory cell may be in one of a plurality of memory states (also referred to as data states). The memory states may include an erased state and a plurality of programmed states. The number of programmed states corresponds to the number of bits the memory cells are programmed to store.	133	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A memory cell programmed to store four bits may be in an erased state 402 or one of fifteen programmed states A-O. Each cell threshold voltage distribution curve (within states Er-O) is associated with the erased state or one of the programmed states. Additionally, each threshold voltage distribution curve defines and/or is associated with a distinct threshold voltage range that, in turn, defines, is assigned, or is associated with a distinct one of a plurality of predetermined n-bit binary values. As such, determining what threshold voltage VTH a memory cell has enables the data (i.e., the logic values of the bits) that the memory cell is storing to be determined.	134	Added by DJM 12 2021	12/22/21, 12:00 AM

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