New Paragraph

Paragraphs
Actions Application Content Paragraph Number Notes Modified
View Edit
Delete 		US10998041B1 The volatile memory 1518 and the non-volatile memory 1520 may include a number of memories including a main random access memory (RAM) for storage of instructions and data during program execution and a read only memory (ROM) in which read-only non-transitory instructions are stored. The volatile memory 1518 and the non-volatile memory 1520 may include a file storage subsystem providing persistent (non-volatile) storage for program and data files. The volatile memory 1518 and the non-volatile memory 1520 may include removable storage systems, such as removable FLASH memory. 266 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 The bus subsystem 1516 provides a mechanism for enabling the various components and subsystems of data processing system 1502 communicate with each other as intended. Although the communication network interface 1506 is depicted schematically as a single bus, some embodiments of the bus subsystem 1516 may utilize multiple distinct busses. 267 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 It will be readily apparent to one of ordinary skill in the art that the computing device 1500 may be a device such as a smartphone, a desktop computer, a laptop computer, a rack-mounted computer system, a computer server, or a tablet computer device. As commonly known in the art, the computing device 1500 may be implemented as a collection of multiple networked computing devices. Further, the computing device 1500 will typically include operating system logic (not illustrated) the types and nature of which are well known in the art. 268 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 Terms used herein should be accorded their ordinary meaning in the relevant arts, or the meaning indicated by their use in context, but if an express definition is provided, that meaning controls. 269 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 Within this disclosure, different entities (which may variously be referred to as "units," "circuits," other components, etc.) may be described or claimed as "configured" to perform one or more tasks or operations. This formulation--[entity] configured to [perform one or more tasks]--is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be "configured to" perform some task even if the structure is not currently being operated. A "credit distribution circuit configured to distribute credits to a plurality of processor cores" is intended to cover, for example, an integrated circuit that has circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as "configured to" perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible. 270 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 The term "configured to" is not intended to mean "configurable to." An unprogrammed FPGA, for example, would not be considered to be "configured to" perform some specific function, although it may be "configurable to" perform that function after programming. 271 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 As used herein, the term "based on" is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase "determine A based on B." This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on." 272 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase "perform A in response to B." This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B. 273 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 As used herein, the terms "first," "second," etc., are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. For example, in a register file having eight registers, the terms "first register" and "second register" can be used to refer to any two of the eight registers, and not, for example, just logical registers 0 and 1. 274 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 The read scan circuit 1204 may thus be used by the die controller 1202 to determine the most suitable read levels for memory states as described above for the first read level and the second read level. The die controller 1202 may then interact with the state machine 214 and read/write circuits 208 to set the first read level and the second read level, as well as other determined read levels for the memory states expressed by the memory cells of the non-volatile memory array 206. These set read levels may be used for subsequent read operations. 227 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 In the example of FIG. 11, correlations between one or the other of memory state C and memory state D and one or the other of memory state J and memory state K. In one embodiment, selection of a correlation to use between two states may be based on attributes of the correlations. If the correlations between two states are symmetrical, meaning a correlation from memory state A to memory state J is an inverse of a correlation from memory state J to memory state A, then there are four possible correlations between one or the other of memory state C and memory state D and one or the other of memory state J and memory state K. If the correlations are not symmetrical then there are eight possible correlations. 214 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 In such a situation, the read scan operation may use a correlation that is a most stable correlation between two memory states being considered. "Stable correlation" refers to a correlation that comprises an accuracy rate and/or a set of historical testing or supporting data such that the correlation is true for a majority of instances in the future. 215 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 Based on a stability measure for the possible correlations, a read scan operation may select a first memory state from the two adjacent memory states and a second memory state from the other adjacent memory states associated with the second read level window in response to the first memory state and the second memory state having a stable correlation. In the example illustrated in FIG. 11, between memory states C and D (adjacent memory states) and memory states J and K (other adjacent memory states), there may be between one and eight correlations. If a correlation between memory state C and memory state K is a stable correlation and/or a more stable correlation than other correlations that may be used, the read scan operation may use the correlation between memory state C and memory state K to configure the second read level window 1104. 216 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 FIG. 12 is a block diagram of an exemplary storage device 200. Many of the components comprising the storage device 200 may operate effectively as described with regard to FIG. 1 and FIG. 2. However, the storage device 200 may incorporate a die controller 1202 configured according to one embodiment of the claimed solution. The die controller 1202 may include a state machine 214, a read scan circuit 1204, and a volatile memory 1206. The volatile memory 1206 may be used to access a correlation data structure 1208. 217 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 The non-volatile memory array 206 may be a three-dimensional memory array comprising a number of memory cells. These memory cells may be quad-level cells, such that each memory cell may store four bits of data, as described with regard to FIG. 4 and FIG. 5. The die controller 1202 may be configured to execute storage operations on the memory cells of the non-volatile memory array 206 (three-dimensional memory array). 218 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 The die controller 1202 may cooperate with the read/write circuits 208 to perform memory operations on these memory cells and may include a state machine 214 that provides chip-level control of memory operations. In one embodiment, the read scan circuit 1204 is configured to adjust one or more read levels between memory states. In one embodiment, the read scan circuit 1204 implements a valley search operation to determine whether or not to adjust read levels. 219 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 The read scan circuit 1204 of the die controller 1202 may be configured to iteratively sense a set of memory cells using a first set of candidate read levels until a candidate read level activates a fewest number of memory cells in relation to other candidate read levels within the first set. The read scan circuit 1204 may then determine a first read level for a first memory state based on the candidate read level that activates the fewest number of memory cells. 220 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 A volatile memory 1206 coupled to the read scan circuit 1204 may comprise a correlation data structure 1208 configured to store correlation factors for one or more and potentially each memory state for the set of memory cells. The correlation factors stored in the correlation data structure 1208 may represent correlations between memory states, and multiplying a candidate read level by the correlation factor may modify the candidate read level to account for the correlation. 221 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 The read scan circuit 1204 may in one embodiment be configured to retrieve a correlation between the first memory state and a second memory state. The read scan circuit 1204 may retrieve the correlation from the correlation data structure 1208. Shift correlation table 900 and width correlation table 1000 are two examples of correlation data structure 1208. 222 Added by DJM 12 2021 12/22/21, 12:00 AM
View Edit
Delete 		US10998041B1 Next, the read scan circuit 1204 may determine a second read level for the second memory state using the correlation. This correlation may be stored in the correlation data structure 1208 (e.g., shift correlation table 900 and/or width correlation table 1000) available in volatile memory 1206. Determining a correlation factor may involve the read scan circuit 1204 searching the correlation data structure 1208 based on an identifier (e.g., `Er`, `A`, `B`, `C`, etc.) for one of two adjacent memory states associated with the read level being scanned/checked. The read scan circuit 1204 may then apply the determined correlation factor to the second read level. 223 Added by DJM 12 2021 12/22/21, 12:00 AM

Page 2 of 14, showing 20 record(s) out of 268 total