Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	US10998041B1	This disclosure relates to a method for an improved read scan operation, also referred to as a read level calibration scan. A first read level window, configured to test read levels between two adjacent memory states, is scanned for a first candidate read level that activates the fewest number of memory cells in relation to other candidate read levels within that first read level window. A second read level window for a second candidate read level is then configured based on a correlation between at least one of the two adjacent memory states and one or more other adjacent memory states associated with the second read level window. The second read level window is scanned for a second candidate read level that activates the fewest number of memory cells in relation to other candidate read levels within the second read level window. Finally, a read operation is configured to use the first candidate read level and the second candidate read level.	4	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	This disclosure further relates to an apparatus. This apparatus comprises a three-dimensional memory array of memory cells, a die controller, and a read scan circuit. The die controller is configured to execute storage operations with the memory cells. The read scan circuit iteratively scans a set of memory cells using a first set of candidate read levels until a candidate read level activates the fewest number of memory cells in relation to other candidate read levels within that first set of candidate read levels. The read scan circuit then determines a first read level for a first memory state based on the candidate read level that activates the fewest number of memory cells. The read scan circuit retrieves a correlation between the first memory state and a second memory state. The read scan circuit then determines a second read level for the second memory state using the correlation and sets the first read level and second read level for subsequent read operations.	5	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Finally, this disclosure relates to a system comprising a non-volatile memory array and a storage controller. The non-volatile memory array comprises a plurality of memory dies. The storage controller comprises a read/write circuit, a read scan circuit, an error correction code decoder, and a calibration circuit. The read/write circuit writes data to memory cells of the plurality of memory dies. The read scan circuit implements read scan operations for non-volatile memory array storage blocks. These read scan operations test sets candidate read levels based on correlations between two memory cell memory states for each storage block. The error correction code decoder determines an estimated bit error rate for data read during the read scan operation. The calibration circuit calibrates memory cells based on the read levels determined by the read scan circuit.	6	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS	7	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced.	8	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 1 illustrates a storage system 100 in accordance with one embodiment.	9	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 2 illustrates a storage device 200 in accordance with one embodiment.	10	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 3 illustrates a memory array 300 in accordance with one embodiment.	11	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 4 illustrates cell threshold voltage distribution curves 400 in relation to one embodiment.	12	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 5 illustrates an example encoding for multi-level storage cells 500 in accordance with one embodiment.	13	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 6 illustrates example read scan operation(s) 600.	14	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 7 illustrates correlations between memory states 700 in accordance with one embodiment.	15	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 8 illustrates correlations between memory states 800 in accordance with one embodiment.	16	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 9 illustrates a shift correlation table 900 in accordance with one embodiment.	17	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 10 illustrates a width correlation table 1000 in accordance with one embodiment.	18	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 11 illustrates a read scan operation 1100 in accordance with one embodiment.	19	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 12 illustrates a storage device 200 in accordance with one embodiment.	20	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 13 is a block diagram of an example storage system 1300 in accordance with one embodiment.	21	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 14 illustrates a method for conducting a read scan operation 1400 in accordance with one embodiment.	22	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 15 is an example block diagram of a computing device 1500 that may incorporate certain embodiments.	23	Added by DJM 12 2021	12/22/21, 12:00 AM

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