Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	US10998041B1	The specific relationship between the data programmed into the memory cells and the threshold voltage levels of the memory cell depends on the data encoding scheme used for programming the memory cells. In one example, a gray code scheme may be used to assign data values to the threshold voltage distribution curves. "Gray code encoding" refers to a type of encoding scheme based on a numbering system that assigns a certain bit values to a range of threshold voltages that a memory cell may have. The bit values are assigned such that the bit pattern differs between adjacent threshold voltage ranges by only one bit. Such a bit pattern assignment is advantageous because while a threshold voltage may change, drift, from one range to a neighboring range, unintended change or drift is likely not enough to cause a two bit change in the encoding. In this manner, undesired drift can be detected and accommodated.	135	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one example, the range of threshold voltages may be one of a plurality of threshold voltage ranges that may be used to encode multiple bits of data into a memory cell. For example, suppose a memory cell is configured to store two bits of information, and the successive ranges of threshold voltages are between a negative lower bound threshold voltage and positive upper bound threshold, e.g., about 5 volts. If four ranges are defined the lower most range may have a bit assignment of `00`, the next highest a bit assignment of `01`, the next highest a bit assignment of `10`, and the last range a bit assignment of `10`.	136	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Of course, memory cells that store multiple bits of data may use a gray code encoding or another encoding process, such as those described in US patents: U.S. Pat. No. 6,222,762 and/or U.S. Pat. No. 7,237,074 which are included herein by reference, for all purposes.	137	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 4 illustrates how one example of a gray code encoding maps to the memory states. Below each memory state is a binary value of 4 bits listed from the most significant bit (MSB) reading down to the least significant bit (LSB). FIG. 5 illustrates the same encoding mapping in a table form. A page of data, logical or physical is associated with each position in the binary value. In other words, reading all MSB bits of memory cells along a physical word line, a physical page, or groups of physical pages along a row of the non-volatile memory array forms a logical page.	138	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, the LSB corresponds to a lower most page of data and the MSB corresponds to an upper most page of data, with the other two bits representing intermediate level pages of data. In certain embodiments, a multi-level storage cell may adhere to a multi-phase programming model, which includes writing the LSB before the intervening bits and MSB can be written or vice versa. In another embodiment, the LSB, intervening bits, and MSB may be programmed separately by the storage controller. Such an approach may be taken due to vendor or manufacturer requirements for page pairing (e.g., an LSB bit of MLC cell is paired with an MSB bit of a different MLC cell) and page addressing (e.g., LSB page is be programmed before the MSB page or vice versa). In certain instances, the LSB is written before the MSB is written, the MSB is written before the LSB is written, or the like.	139	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 5 illustrates example encoding for multi-level storage cells 500. Using a gray code encoding enables a logical page to be read with fewer read operations because the encoding ensures that only on bit changes between adjacent memory states. For example, the erased state Er may be represented by "1111" and may transition to memory state A to represent "1110", in which the bit that changed is the least significant bit. FIG. 5 illustrates four pages Page 1 504, Page 2 506, Page 3 508, and Page 4 510. Each page may be read one at a time. For example, Page 1 504 may be read, then Page 2 506, etc., and four page reads may thus be needed to determine which of the QLC memory states 502 is represented at a particular memory cell.	140	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Due to the gray code encoding, bits stored in a cell may be determined by reading at the locations where bits may change between memory states. For example to read Page 1 504, read operations at read level A 406, read level D 412, read level F 416, and read level K 426 are a sufficient number of reads to decode the data values for Page 1 504 without reading at each default read level.	141	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 6 illustrates example read scan operation(s) 600 on memory cells programmed to one of sixteen possible memory states, e.g., Er-O. A read scan operation may adjust read levels from a default read level to a new read level in order to reduce a number of errors when reading the memory cells.	142	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Read scan operation" refers to a maintenance operation performed to identify and mitigate or avoid or counter errors in the data or storage cells and/or other components of a non-volatile storage device. A read scan operation may be referred to, interchangeably, as a "read scan" or "read scan operation." In one embodiment, a read scan operation involves reading data from, or sensing a determinable physical characteristic, or a memory state of storage cells in a storage block. Next, the read scan operation checks the memory states of the storage cells for any errors, corrects as many errors as possible, and determines a bit error rate. Then, the read scan operation determines if the bit error rate satisfies a threshold such as a read bit error rate threshold.	143	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, the read scan operation reads data from each logical page, or word line, of the storage block. In another embodiment, the read scan operation selects less than all of the logical pages of the storage block. In other words, the read scan operation may sample the logical pages of the storage block from which to read data for the read scan operation.	144	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	If a read bit error rate threshold is satisfied, the read scan operation then may perform a data scrub operation or a data refresh operation. In certain embodiments, a read scan operation may always include a data scrub operation or a data refresh operation. In other embodiments, performing a data scrub operation or data refresh operation may be conditioned on the bit error rate satisfying a read bit error rate threshold. In such embodiments, a read scan operation may be referred to as a "read scrub" or "read scrub operation." In these embodiments, a read scan operation may conditionally include a data scrub operation.	145	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In certain embodiments, a read scan operation may operate as a foreground process meaning that the read scan operation interrupts, or delays, a non-volatile storage device from servicing read commands or write commands for a host. In addition, the read scan operation may need to complete working on a particular storage block and thereby delay a host read command for data on that particular storage block. Thus, in such embodiments, a read scan operation may impact quality of service levels between a host and the non-volatile storage device.	146	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A read scan operation may use a variety of techniques and/or methods to adjust read levels. Certain of the techniques or methods may iteratively use different candidate read levels in order to determine a replacement read level for a current read level. Furthermore, a read scan operation may be implemented in a storage controller, die controller, host 106, or combination of these.	147	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Candidate read level" refers to a value, setting, configuration, numeric value, offset, or the like for a read level that may provide more accurate sensing of memory cells and/or reading of data from memory cells than a current read level. In certain embodiments, candidate read levels may be predetermined, and may be stored in a repository such as a data structure. In other embodiments, candidate read levels may be predetermined and may be organized into a predefined order which a read scan circuit may be configured to follow in selecting candidate read levels to use in determining a read level to replace a current read level.	148	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In still other embodiments, candidate read levels may be calculated based on results of one or more prior sense, and/or read operations (referred to herein as a "scan" or "scans"), that a read scan circuit may perform on a set of storage cells. For example, in one embodiment, the read scan circuit may compare results of a prior scan to results for a current scan using a current candidate read level. If the results with the current candidate read level are more favorable, the read scan circuit may calculate a next candidate read level based on the current candidate read level. If the results with the current candidate read level are less favorable, the read scan circuit may calculate a next candidate read level based on one or more prior scans using candidate read levels. In embodiments that determine which candidate read levels to use with successive iterations, a read scan circuit may apply a positive or negative offset to a current read level to determine a next candidate read level.	149	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A candidate read level may comprise one of a plurality of read levels positioned generally between a majority of memory cells of cell threshold voltage distributions for two adjacent memory states. It is desirable that candidate read levels result in optimal performance when reading data from memory cells programmed to one of the two adjacent memory states.	150	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, at least one of the candidate read levels will produce an optimal result, result in the fewest number of bit errors when reading from one of the adjacent memory states. Such candidate read levels may be referred to as a target read level. A target read level is a read level that results in a smallest or fewest number of activated memory cells in relation to other candidate read levels that may be iteratively checked. In another embodiment, the target read level is a read level that results in a smallest or fewest number of bit errors or bit error rate or estimated bit error rate from a read set of memory cells in relation to other candidate read levels that may be iteratively checked.	151	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Valley Search Operation	152	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	One method a read scan operation may use is referred to as a valley search operation. "Valley search operation" refers to is a type of read scan operation configured to iteratively test or check a number of candidate read levels around a boundary for a set of memory cells within cell threshold voltage distributions for two adjacent memory states. In certain embodiments, the valley search operation may begin with a current read level or a default read level which may have been set when a storage device is manufactured. Next the valley search operation may apply a candidate read level to determine if the candidate read level resulted in fewer memory cells activating than the current read level. If so, this means that more memory cells will be identified as being programmed to a correct memory state. If not, this means that more memory cells will be erroneously identified as being to one of the adjacent memory states. The valley search operation continues to iterate in this manner changing the candidate read level with each iteration until a read level is identified that results in the fewest number set of memory cells being activated and/or a fewest number of read errors (e.g., lower bit error rate). In this manner, the valley search operation seeks a target candidate read level that provides an optimal read result. The valley search operation gets its name from the iterative process of testing candidate read levels until one is located that aligns with a "valley" between cell threshold voltage distribution curves for two adjacent memory states.	153	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In one embodiment, a valley search operation may be conducted to adjust read levels for a lowest logical page, Page 1 504, and/or for sets of adjacent memory states for each logical page. Details for a valley search operation for Page 1 504 are illustrated to provide an example.	154	Added by DJM 12 2021	12/22/21, 12:00 AM

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