Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	US10998041B1	The binary values for memory cells storing data of Page 1 504 are illustrated below the curves. As these values indicate and the gray code encoding shows four read operation are needed to read Page 1 504. In one embodiment, a valley search operation may check, and optionally adjust, each of the four read levels. Each read level may be associated with a read level window.	155	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	"Read level window" refers to a set of candidate read levels that may serve as a read level between two adjacent memory states. In certain embodiments, where the memory cells that are read a read using one or more threshold voltages, a read level window may comprise a set of threshold voltages between a low threshold voltage and a high threshold voltage, with each member of the set of candidate read levels within the read level window comprising a distinct threshold voltage.	156	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In another embodiment comprise NAND memory cells, a read level window may comprise a set of threshold voltages between a low threshold voltage and a high threshold voltage, with each member of the set of candidate read levels within the read level window comprising a threshold voltage offset by one or more offset amounts from a default read level, such as a current read level. The offsets from the default read level may be both greater than and/or less than the default read level. A read level window may also be referred to as a "scanning" window.	157	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 6 includes read level window 602, read level window 604, read level window 606, and read level window 608, one for each read level A 406, read level D 412, read level F 416, and read level K 426, respectively. For each read level window, scanning window, a set of sets of candidate read levels 610 may be used. For example, threshold voltage levels #1-#7 may be the candidate read levels used across read level window 602 to determine an optimal placement for read level A 406, levels #8-14 for read level D 1110, levels #15-21 for read level F 416, and levels #22-28 for read level K 1114.	158	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	By way of example, a valley search operation may iteratively determine an optimal read level for each of read level A 406, read level D 412, read level F 416, and read level K 426. For read level A 406, suppose the default read level is candidate read level #5 and memory state Er has moved up, shifted to the right and memory state A has shifted to the left, moved down. After determining how many memory cells candidate read level #5 activates (or alternatively how many bit errors are in a code word when read level A 406 is a candidate read level #5), the valley search operation may next check a next highest candidate read level #6 or check a next lowest candidate read level #4.	159	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	With each iterative check, the valley search operation compares a result (e.g., number of activated memory cells or bit error rate) with a prior result for a previous check. If the candidate read level being checked/tested results in higher bit errors or more activated memory cells, the valley search operation may check a threshold voltage in an opposite direction than the direction that lead to the higher bit errors (activated memory cells). So, if the candidate read level #5 results in fewer activated memory cells than candidate read level #6, then the valley search operation may next test candidate read level #4. If the candidate read level #4 results in fewer activated memory cells than candidate read level #5, then the valley search operation may next test candidate read level #3. If the candidate read level #3 results in more activated memory cells than candidate read level #4, then the valley search operation may stop iterating and determine that candidate read level #4 is the "valley" between the Er memory state and A memory state. Consequently, the valley search operation may change a default read level from candidate read level #5 to candidate read level #4. Next, the valley search operation may follow this similar process for read level D 412, read level F 416, and read level K 426. For example, candidate read levels from read level window 604, read level window 606, and read level window 608 may be iteratively tested. Furthermore, of a valley search operation is done for all logical pages, eventually, all the read levels of the Vt window will be tested and potentially changed to obtain optimal read operation results. A valley search operation is an iterative trial and error method for determining how to adjust read levels.	160	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	The candidate read levels, for example of read level window 602, may be predefined. In another example, the valley search operation derives the candidate read levels by applying an offset for a last candidate read level.	161	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Bit Error Rate Estimation (BES)	162	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Another read scan operation that may be used is referred to as a Bit Error Rate Estimation (BES) method. "Bit error rate" refers to a measure of a number of bits in error of a total overall number of bits processed. Depending on the use case, a bit error rate may be calculated either before, or after, an Error Correction Code (ECC) decoder has made one or more attempts to correct one or more bits in error.	163	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	Like a valley search operation, a BES read scan operation is an iterative trial and error method that seeks to determine an optimal read level for one or more read levels. Similarly, to set read levels for Page 1 504, a BES read scan operation may check read level A 406, read level D 412, read level F 416, and read level K 426. However, a BES read scan operation may be optimized to determine a most likely optimal candidate read level for each read level and as the BES read scan operation tests for one read level, an emulator may determine the results of scanning Page 1 504 with the other read levels set a certain starting levels. In one embodiment, the scanning may be different from reading because threshold voltages determined are emulated and data from memory cells is not actually read, in the normal sense. Use of aspects of the disclosed solution may enable a BES read scan operation to read at the read levels but perform fewer emulated threshold voltage determinations in the scanning part of the BES read scan operation. In this manner, the BES read scan operation seeks to limit a number of iterations of read/sense operations performed on the memory cells to determine optimal read levels.	164	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	BES read scan operations may start with all read levels at a predetermined starting point and take sensed measurements for different candidate read levels for a first read level. For example, a BES-based scan may begin at #4 for read level A 406, then iterate in a predefined order (#3, then #5, then #6, then #2, etc.) through the candidate read levels of read level window 602 while keeping other read levels (read level D 1110, read level F 416, and read level K 1114) in the same position. "Predefined order" refers to a sequence of steps, operations, selections, functions, determination, or actions in an order that is defined before an operation that follows the predefined order is initiated.	165	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	These other read levels may be emulated rather than sensed. When a minimum (fewest number of memory cells activated or fewest number of bit errors) has been indicated among the first set of sets of candidate read levels 610, determining read level A 406, the next set of candidate read levels for a next read level may be analyzed. In certain instances, minimum here relates to a minimum number of check nodes (syndrome weights), which may be used as an estimate of BER based on different hypotheses related to the number of senses performed. To obtain syndrome weights, a BES read scan operation may read and decode data using a decoder, and this process may take significant time.	166	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	When the syndrome weights are below a threshold, the relative value of a syndrome weights is a suitable proxy or indicator for a bit error rate. In this manner, the BES read scan operation leverages an estimated bit error rate. "Estimated bit error rate" refers to a value that directly, indirectly, and/or approximately represents a bit error rate for a certain set of data bits stored in one or more memory cells. Advantageously, an estimated bit error rate serves as a suitable proxy for a calculated bit error rate and may be obtained with fewer computing cycles and in a faster time than time needed to determine a bit error rate.	167	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	One example of an estimated bit error rate is a rate resulting from a Bit Error Rate (BER) Estimation Scan (BES) operation. A BES read scan operation is a type of read scan operation in with candidate read levels for certain read levels for a logical page a tested in a predefined order. In one embodiment, the BES read scan operation tests a particular candidate read level and an algorithm determines results for simulated/emulated testing of other read levels for a particular logical page.	168	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	A BES read scan operation, in one embodiment, may determine an estimated bit error rate by comparing syndrome weights between iterative read level sensing or read operations to determine which candidate read level results in the fewest number of activated memory cells. In such embodiments, a syndrome weight below a threshold serves as a proxy for a bit error rate, an estimated bit error rate. A syndrome weight is a number of unsatisfied ECC parity check equations nodes/equations from a Low-Density Parity-Check (LDPC) error correction code decoder (ECC decoder).	169	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In a Low-Density Parity-Check (LDPC) ECC decoder, a syndrome weight for a codeword is a number of unresolved equations, or unsatisfied check nodes, when the codeword is decoded. On average, the greater the number of unsatisfied check nodes (higher syndrome weight) the higher the number of errors in the codeword. On average, the fewer the number of unsatisfied check nodes (higher syndrome weight) the lower the number of errors in the codeword. Thus, in certain instances, a codeword with fewer errors may still have a greater the number of unsatisfied check nodes (higher syndrome weight).	170	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	In addition, a BES read scan operation may test candidate read levels in a predefined order. For example, when checking for read level D 412, the predefined order of candidate read levels may be #10, then #13, then #14, then #8, then #9. This predefined order may be determined by a manufacturer based on a series of tests and research and development to understand which candidate read levels are most likely to result in the lowest bit error rate after the fewest number of iterations within the BES read scan operation.	171	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	There are various other aspects to the BES read scan operation which are not discusses in detail here. Instead, suitable implementations of a BES read scan operation for use with aspects of the disclosed solution are described in U.S. Pat. No. 9,697,905 filed Dec. 4, 2014, issued Jul. 4, 2017, which is hereby incorporated by reference for all purposes	172	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	FIG. 7 depicts an example of correlations between memory states 700 and adjustments to read levels for a set of multi-level storage cells of non-volatile memory media. Those of skill in the art recognize that threshold voltages for memory cells change over time due to various factors, including temperature changes, wearing of the memory cells, disturb influences, leakage, and the like. Generally, such changes are not problematic for a majority of the memory cells within a cell threshold voltage distribution. However, these changes in threshold voltage may result in higher bit error rates due to memory cells near the boundaries of the memory states (such boundaries may be referred to a lower tail for a part of the distribution curve closest to the lowest threshold voltages and an upper tail a part of the distribution curve closest to the higher threshold voltages) moving from having a threshold voltage within one memory state to having a threshold voltage within a neighboring memory state (adjacent memory state).	173	Added by DJM 12 2021	12/22/21, 12:00 AM
View Edit Delete	US10998041B1	To address these changes, the read scan operation adjusts the read levels at the cell threshold voltage distribution curve boundaries. FIG. 7 illustrates a few example memory states in which the read level adjustment has been made. Curves illustrated in solid lines represent a current distribution and those illustrated in dashed lines represent what the cell threshold voltage distribution was in the past.	174	Added by DJM 12 2021	12/22/21, 12:00 AM

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