16869424

Paragraph Number

122

In certain embodiment, these countermeasures may include adjusting configuration parameters such that a bit error rate decreases. In certain embodiments, the steps of determining a cell threshold voltage distribution, checking read levels and other media characteristics with respect to bit error rate, and taking any countermeasures, may be referred to as a CVD scan, a read scan, or a read scan operation. A CVD scan may require significant time to complete due to the various steps involved and the number of memory cells being scanned. In particular, where memory cells store four or more bits per memory cell, a CVD scan may incur high latency, unless aspects of the claimed solution are used. "Bit error rate" refers to a measure of a number of bits in error of a total overall number of bits processed. Depending on the use case, a bit error rate may be calculated either before, or after, an Error Correction Code (ECC) decoder has made one or more attempts to correct one or more bits in error.

Added by DJM 12 2021