16455676

Paragraph Number

63

The method also includes forming a passivation layer over each of the plurality of semiconductor die. The passivation layer may protect the semiconductor device from corrosion. In various implementations, the passivation layer may include, by non-limiting example, oxides, nitrides, polyimides and any other material capable of protecting the surface of the semiconductor die. Referring to FIG. 16, the plurality of semiconductor die 52 are illustrated after formation of the passivation layer 64. As illustrated, the passivation layer 64 covers the first side of each of the semiconductor die and also covers the sidewalls of the semiconductor die. The passivation layer couples with the optically transmissive substrate and encapsulates the first RDL and the second RDL. In various implementations, the method includes coupling one or more interconnects with the first side of the semiconductor die. As illustrated in FIG. 17, the interconnects may include a plurality of solder balls 66. The placement and coupling the solder balls 66 may include patterning and etching steps of the passivation layer material to expose the contacts/pads to which the solder balls couple (and some deposition steps if underbump metallizations are employed). In other implementations, the interconnects may include ball grid arrays, copper pillars, or other electrically conductive material for surface mount devices.

Added by DJM 3 2021