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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
63
Application Number
16455676
Reference Case 1
Reference Case 2
Content
The method also includes forming a passivation layer over each of the plurality of semiconductor die. The passivation layer may protect the semiconductor device from corrosion. In various implementations, the passivation layer may include, by non-limiting example, oxides, nitrides, polyimides and any other material capable of protecting the surface of the semiconductor die. Referring to FIG. 16, the plurality of semiconductor die 52 are illustrated after formation of the passivation layer 64. As illustrated, the passivation layer 64 covers the first side of each of the semiconductor die and also covers the sidewalls of the semiconductor die. The passivation layer couples with the optically transmissive substrate and encapsulates the first RDL and the second RDL. In various implementations, the method includes coupling one or more interconnects with the first side of the semiconductor die. As illustrated in FIG. 17, the interconnects may include a plurality of solder balls 66. The placement and coupling the solder balls 66 may include patterning and etching steps of the passivation layer material to expose the contacts/pads to which the solder balls couple (and some deposition steps if underbump metallizations are employed). In other implementations, the interconnects may include ball grid arrays, copper pillars, or other electrically conductive material for surface mount devices.
Notes
Added by DJM 3 2021
Raw Data
<w:p w14:paraId="517CEA08" w14:textId="0FF6020D" w:rsidR="00514A7C" w:rsidRDefault="001A03CE" w:rsidP="002377AC"><w:pPr><w:numPr><w:ilvl w:val="0"/><w:numId w:val="7"/></w:numPr><w:overflowPunct w:val="0"/><w:autoSpaceDE w:val="0"/><w:autoSpaceDN w:val="0"/><w:adjustRightInd w:val="0"/><w:spacing w:line="480" w:lineRule="auto"/><w:rPr><w:szCs w:val="24"/></w:rPr></w:pPr><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>The method also includes forming a passivation layer over each of the plurality of semiconductor die. The passivation layer may protect the semiconductor device from corrosion. In various implementations, the passivation layer may include</w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>, by non-limiting example,</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> oxides</w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>,</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> nitrides</w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>, polyimides and any other material capable of protecting the surface of the semiconductor die</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">. Referring to </w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>FIG</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">. 16, the plurality of semiconductor die </w:t></w:r><w:r w:rsidR="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>5</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">2 are illustrated after formation of the passivation layer 64. As illustrated, the passivation layer </w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">64 </w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">covers the first side of each of the semiconductor die and also covers the sidewalls of the semiconductor die. The passivation layer couples with the optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> substrate and encapsulates the first RDL and the second RDL. In various implementations, the method includes coupling one or more interconnects with the first side of the semiconductor die. As illustrated in FIG. 17, the interconnects may include a plurality of solder balls</w:t></w:r><w:r w:rsidR="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 66</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">. </w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">The </w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:lastRenderedPageBreak/><w:t xml:space="preserve">placement and coupling the solder balls 66 may include patterning and etching steps of the passivation layer material to expose the contacts/pads to which the solder balls couple (and some deposition steps if </w:t></w:r><w:proofErr w:type="spellStart"/><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>underbump</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> </w:t></w:r><w:proofErr w:type="spellStart"/><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>metallizations</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> are employed). </w:t></w:r><w:r w:rsidR="00514A7C"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">In other implementations, the interconnects may include ball grid arrays, copper pillars, or other electrically conductive material for surface mount devices. </w:t></w:r></w:p>
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