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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
64
Application Number
16455676
Reference Case 1
Reference Case 2
Content
The method includes singulating through the passivation layer and the optically transmissive substrate to form a plurality of semiconductor packages. In various implementations, singulating may be performed through, by non-limiting example, sawing, laser cutting, any combination thereof, and other methods for singulating through materials such as glass, metal, plastics, and/or semiconductor materials. Referring to FIG. 18, an implementation of a semiconductor package 68 after singulation is illustrated. As previously described, the semiconductor package 68 includes a first RDL 70 and a second RDL 72 to provide electrical connectivity to the device without the use of TSVs. The first RDL 72 is coupled to the optically transmissive lid 74. In various implementations, the optically transmissive lid may include, by non-limiting example, glass, polycarbonate, acrylic, plastics, or other materials that allow some or all of a desired wavelength of light to pass through the material. The first RDL is also mechanically and electrically coupled with inner bumps 76 which are coupled to the second side of the semiconductor die 78 through die pads 80. In various implementations, two or more die pads are positioned around the active area of the die. The active area 82 of the die 78 may include a sensor area of an image sensor die. The semiconductor die is encapsulated in an isolation layer 84. The semiconductor device including the first RDL 70, second RDL 72, and the isolation layer 84 are encapsulated in a passivation layer 86. In this particular implementation, solder balls are coupled to the second RDL through openings in the passivation layer. In various implementations, other surface mount connection types (pins, studs, stud bumps, pads, etc.) may be used.
Notes
Added by DJM 3 2021
Raw Data
<w:p w14:paraId="24D5D0EB" w14:textId="04A147A1" w:rsidR="001A03CE" w:rsidRPr="002377AC" w:rsidRDefault="00514A7C" w:rsidP="00C72FBE"><w:pPr><w:numPr><w:ilvl w:val="0"/><w:numId w:val="7"/></w:numPr><w:overflowPunct w:val="0"/><w:autoSpaceDE w:val="0"/><w:autoSpaceDN w:val="0"/><w:adjustRightInd w:val="0"/><w:spacing w:line="480" w:lineRule="auto"/><w:rPr><w:szCs w:val="24"/></w:rPr></w:pPr><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">The method includes singulating through the passivation layer and the optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> substrate to form a plurality of semiconductor packages. In various implementations, singulating may be performed through</w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>, by non-limiting example,</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> sawing, laser cutting, </w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">any combination thereof, </w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">and other methods for singulating </w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">through materials such as glass, </w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>metal</w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">, plastics, </w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>and/</w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>or semiconductor material</w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>s</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>. Referring to FIG. 18, an implementation of a semiconductor package 68 after singulation is illustrated. As previously described, the semiconductor package 68 includes a first RDL</w:t></w:r><w:r w:rsidR="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 70</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> and a second RDL </w:t></w:r><w:r w:rsidR="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">72 </w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">to provide electrical connectivity to the device without the use of TSVs. </w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>The first RDL</w:t></w:r><w:r w:rsidR="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 72</w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> is coupled to the optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> lid 74. In various implementations, the optica</w:t></w:r><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">lly </w:t></w:r><w:proofErr w:type="spellStart"/><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r w:rsidR="00273652"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> lid may include, by non-limiting example,</w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> glass</w:t></w:r><w:r w:rsidR="00051659" w:rsidRPr="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>,</w:t></w:r><w:r w:rsidR="00C72FBE" w:rsidRPr="00C72FBE"><w:t xml:space="preserve"> </w:t></w:r><w:r w:rsidR="00C72FBE" w:rsidRPr="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>polycarbonate, acrylic, plastics, or other materials that allow some or all of a desired wavelength of light</w:t></w:r><w:r w:rsidR="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> to pass through the material. </w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>The first RDL is also mechanically and electrically coupled with inner bumps 76 which are coupled to the second side of the semiconductor die 78 through die pads</w:t></w:r><w:r w:rsidR="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 80</w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>. In various implementations, two or more die pads are positioned around the active area of the die. The active area 82 of the die 78 may include a sensor area of an image sensor die. The semiconductor die is encapsulated in an isolation layer 84. The semiconductor device including the first RDL</w:t></w:r><w:r w:rsidR="00083CD7"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 70</w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>, second RDL</w:t></w:r><w:r w:rsidR="00083CD7"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> 72</w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">, and </w:t></w:r><w:r w:rsidR="00C72FBE"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">the </w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">isolation layer 84 are encapsulated in a passivation layer 86. In this particular implementation, solder balls are coupled to the second </w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:lastRenderedPageBreak/><w:t xml:space="preserve">RDL through </w:t></w:r><w:r w:rsidR="00083CD7"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">openings in </w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>the passivation layer. In various implementations,</w:t></w:r><w:r w:rsidR="00083CD7"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> other surface mount connection types (pins, studs, stud bumps, pads, etc.)</w:t></w:r><w:r w:rsidR="00051659"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> may be used. </w:t></w:r></w:p>
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