Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	US-8380915-A1	The encryption key may be received from a client 114, another computer, key manager, or other device that holds the encryption key to be used to encrypt the data segment. In one embodiment, encryption keys are transferred to the solid-state storage controller 104 from one of a solid-state storage device 102, computer 112, client 114, or other external agent which has the ability to execute industry standard methods to securely transfer and protect private and public keys.	119	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the write data pipeline 106 also includes an encryption module 314 that encrypts a data or metadata segment received from the input buffer 306, either directly or indirectly, prior sending the data segment to the packetizer 302, the data segment encrypted using an encryption key received in conjunction with the data segment. The encryption keys used by the encryption module 314 to encrypt data may not be common to all data stored within the solid-state storage device 102 but may vary on an per data structure basis and received in conjunction with receiving data segments as described below. For example, an encryption key for a data segment to be encrypted by the encryption module 314 may be received with the data segment or may be received as part of a command to write a data structure to which the data segment belongs. The solid-sate storage device 102 may use and store a non-secret cryptographic nonce in each data structure packet that is used in conjunction with the encryption key. A different nonce may be stored with every packet. Data segments may be split between multiple packets with unique nonces for the purpose of improving protection by the encryption algorithm.	118	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the bias module 318 may be integrated with another element of the write data pipeline 106, such as the compression module 312, the encryption module 314, the ECC encoder 304, or the like. The bias module 318 and corresponding inverse bias module 332 transparently increase the performance of the solid-state storage media 110 as the bias module 318 biases data packets before they are written and the inverse bias module 332 converts the biased data packets back to their original source state after they are read.	117	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the bias module 318 biases one or more data segments prior to sending the data segments to the ECC encoder 304. The data segment may be a grouping of bits smaller than a data packet in one embodiment. In such an embodiment, the data segment may comprise the width in bits/bytes of the write data pipeline 106. Similarly, the inverse bias module 332 may convert biased data segments back to their original source state after they are read. Biasing and inverse biasing a data segment may facilitate use of the bias module 318 and the inverse bias module 332 in a write data pipeline 106 and a read data pipeline 108 because the data segment may be sized to match the size (bus width) of data streaming through the pipelines 106,108.	116	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Once a section of storage has been marked for recovery, valid packets in the section typically must be relocated. The garbage collector bypass 316 allows packets to be read into the read data pipeline 108 and then transferred directly to the write data pipeline 106 without being routed out of the solid-state storage controller 104. In one embodiment, the garbage collector bypass 316 is part of an autonomous garbage collector system that operates within the solid-state storage device 102. This allows the solid-state storage device 102 to manage data so that data is systematically spread throughout the solid-state storage media 110 to improve performance, data reliability and to avoid overuse and underuse of any one location or area of the solid-state storage media 110 and to lengthen the useful life of the solid-state storage media 110.	125	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	By biasing data packets toward the bias of the storage cells, the bias module 318 increases performance and endurance of the solid-state storage media 110 and the solid-state storage device 102. For example, biasing packets to more closely match the bias of the storage cells decreases write times and erase times because fewer actual storage cells must be changed to execute the operation. It also increases the writable life of the storage cells because fewer operations that are executed on a storage cell mean that the storage cell will last longer before wear begins to affect the storage cell performance/reliability. In certain embodiments, biasing data packets may decrease power consumption or have other additional benefits. Because, in one embodiment, the storage cells store initial binary values that satisfy a bias just prior to being programmed or written to, the closer that the data packets match the bias of the storage cells, the fewer the number of storage cells that are changed to store the data packets, and the more storage cells that remain in a biased state.	114	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Those of skill in the art recognize that the bias module 318 may, alternatively, operate on one or more data segments that form a subset of a data packet. Similarly, the inverse bias module 332 may operate on data segments as well. Alternatively, or in addition, in one embodiment, the data packet (or data packet subsets such as a data segment) may be sized based on a size of a storage region in the solid-state storage media 110, a size of a bus or buffer, a size of a pipeline 106, 108, a number of extra bits available for storage of an indicator, or the like.	113	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The bias module 318 biases a packet by changing a bias of the packet to more closely match a bias of the storage cells of the solid-state storage media 110. The bias module 318 biases the packets in a reversible manner, such that the inverse bias module 332 can convert the packets back to their original source data values with their original source biases. In one embodiment, the packets that the bias module 318 biases are sized for storage in a specific logical or physical storage region or division of the solid-state storage media 110, such as an erase block, a virtual erase block, a page, a virtual page, an ECC chunk, a division within a page, or the like. In one embodiment, the bias module 318 selectively biases certain packets based on a bias of the packets, and may not bias other packets.	112	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the bias module 318 biases source data to reduce inter-cell interference as a separate step performed separately from, instead of, or in addition to other biasing techniques. For example, upon flipping, whitening, compressing, relocating, and/or otherwise biasing source data, separate blocks of source data may still exhibit patterns that cause inter-cell interference, and the bias module 318 may bias one or more of the separate blocks of source data toward a pattern that minimizes inter-cell interference, or the like.	111	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	For certain types of storage cells, such as SLC flash memory, the voltage level of a storage cell and associated voltage differentials between storage cells may be based on a single bit value for each storage cell and biasing data may include biasing toward a binary pattern with minimal transitions between binary one values and binary zero values within a data packet and/or within a physical region of storage cells. For other types of storage cells, such as MLC flash memory, the voltage level of a storage cell and associated voltage differentials between storage cells may be based on groups of bits forming a sub-pattern or symbol, and biasing data may include biasing toward a binary pattern with minimal transitions between certain sub-patterns or symbols. One example of using sub-patterns or symbols includes binary or Gray-code mapping of multiple binary values to associated charge levels within MLC storage cells. The bits stored by a single MLC storage cell, in certain embodiments, may not have adjacent addresses, but may be stored on different physical pages, logical pages, or the like.	110	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In addition to local types of inter-cell interference, larger multi-cell structures, such as bit strings, word lines, or the like, may experience inter-cell interference. Certain stripes or other patterns in data, such as stripes of binary ones or of binary zeroes, may interfere with the accuracy or effectiveness of sense amplifiers and/or other management circuitry for these larger, multi-cell structures, and it may be advantageous to bias data away from such stripes or other patterns.	109	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In certain embodiments, a bias of one or more storage cells may be influenced by or based on a state of other storage cells physically adjacent to or otherwise in proximity to the one or more storage cells. For example, it may be desirable to bias data stored in storage cells to minimize inter-cell interference between the storage cells and other storage cells, or the like. Inter-cell interference can be caused by voltage differentials between physically adjacent storage cells and, in certain embodiments, biasing data to reduce or minimize the voltage differentials between storage cells based on a physical geometry of the storage cells can reduce inter-cell interference. In one embodiment, storage cells of the solid-state storage media 110 may have a bias toward a binary pattern that satisfies a predefined voltage differential threshold between the storage cells and other physically adjacent storage cells, or the like.	108	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	For example, in one embodiment, the storage cells of the storage elements 216, 218, 220 may each store a binary value of one upon delivery from a manufacturer, and may each be erased to a value of one prior to being programmed, or written to, as is typical with flash memory. In another embodiment, the storage cells of the storage elements 216, 218, 220 may be biased toward binary zeroes, toward a balance or equal amount of binary ones and zeroes, toward a certain binary value for a plurality of bits, toward a binary pattern, or the like.	107	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Read Data Pipeline	134	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the read data pipeline 108 includes an output buffer 330 that receives requested packets from the alignment module 326 and stores the packets prior to transmission to the requesting device 155. The output buffer 330 accounts for differences between when data segments are received from stages of the read data pipeline 108 and when the data segments are transmitted to other parts of the solid-state storage controller 104 or to the requesting device 155. The output buffer 330 also allows the data bus 204 to receive data from the read data pipeline 108 at rates greater than can be sustained by the read data pipeline 108 in order to improve efficiency of operation of the data bus 204.	143	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the read data pipeline 108 includes a read synchronization buffer 328 that buffers one or more requested packets read from the solid-state storage media 110 prior to processing by the read data pipeline 108. The read synchronization buffer 328 is at the boundary between the solid-state storage clock domain and the local bus clock domain and provides buffering to account for the clock domain differences.	142	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The alignment module 326 re-formats the data as data segments of a data structure in a form compatible with a device requesting the data segment prior to forwarding the data segment to the next stage. Typically, as data is processed by the read data pipeline 108, the size of data segments or packets changes at various stages. The alignment module 326 uses received data to format the data into data segments suitable to be sent to the requesting device 155 and joined to form a response. For example, data from a portion of a first data packet may be combined with data from a portion of a second data packet. If a data segment is larger than a data requested by the requesting device 155, the alignment module 326 may discard the unwanted data.	141	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The read data pipeline 108 includes an alignment module 326 that receives data from the depacketizer 324 and removes unwanted data. In one embodiment, a read command sent to the solid-state storage media 110 retrieves a packet of data. A device requesting the data may not require all data within the retrieved packet and the alignment module 326 removes the unwanted data. If all data within a retrieved page is requested data, the alignment module 326 does not remove any data.	140	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The read data pipeline 108 includes a depacketizer 324 that receives ECC blocks of the requested packet from the ECC decoder 322, directly or indirectly, and checks and removes one or more packet headers. The depacketizer 324 may validate the packet headers by checking packet identifiers, data length, data location, etc. within the headers. In one embodiment, the header includes a hash code that can be used to validate that the packet delivered to the read data pipeline 108 is the requested packet. The depacketizer 324 also removes the headers from the requested packet added by the packetizer 302. The depacketizer 324 may directed to not operate on certain packets but pass these forward without modification. An example might be a container label that is requested during the course of a rebuild process where the header information is required for index reconstruction. Further examples include the transfer of packets of various types destined for use within the solid-state storage device 102. In another embodiment, the depacketizer 324 operation may be packet type dependent.	139	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, a corrupted ECC block or portion of a corrupted ECC block of the requested packet that cannot be corrected by the ECC decoder 322 is read by the master controller 224, corrected, and returned to the ECC decoder 322 for further processing by the read data pipeline 108. In one embodiment, a corrupted ECC block or portion of a corrupted ECC block of the requested packet is sent to the device requesting the data. The requesting device 155 may correct the ECC block or replace the data using another copy, such as a backup or mirror copy, and then may use the replacement data of the requested data packet or return it to the read data pipeline 108. The requesting device 155 may use header information in the requested packet in error to identify data required to replace the corrupted requested packet or to replace the data structure to which the packet belongs. In another embodiment, the solid-state storage controller 104 stores data using some type of RAID and is able to recover the corrupted data. In another embodiment, the ECC decoder 322 sends an interrupt and/or message and the receiving device fails the read operation associated with the requested data packet. One of skill in the art will recognize other options and actions to be taken as a result of the ECC decoder 322 determining that one or more ECC blocks of the requested packet are corrupted and that the ECC decoder 322 cannot correct the errors.	138	Added by DJM 3 2021	3/12/21, 12:00 AM

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