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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
94
Application Number
13189402
Reference Case 1
Reference Case 2
Content
The solid-state storage controller 104 may also include control and status registers 340 and control queues 342, a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350. The solid-state storage controller 104, in the depicted embodiment, includes a configuration module 352 that may be part of the write data pipeline 106 and/or part of the read data pipeline 108, or may be independent from the write data pipeline 106 and the read data pipeline 108. The components of the solid-state controller 104 and associated write data pipeline 106 and read data pipeline 108 are described below. In other embodiments, synchronous solid-state storage media 110 may be used and synchronization buffers 308328 may be eliminated.
Notes
Added by DJM 3 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody1"/></w:pPr><w:r><w:t xml:space="preserve">The solid-state storage controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> may also include control and status registers </w:t></w:r><w:r><w:t>340</w:t></w:r><w:r><w:t xml:space="preserve"> and control queues </w:t></w:r><w:r><w:t>342</w:t></w:r><w:r><w:t xml:space="preserve">, a bank interleave controller </w:t></w:r><w:r><w:t>344</w:t></w:r><w:r><w:t xml:space="preserve">, a synchronization buffer </w:t></w:r><w:r><w:t>346</w:t></w:r><w:r><w:t xml:space="preserve">, a storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve">, and a multiplexer (“MUX”) </w:t></w:r><w:r><w:t>350</w:t></w:r><w:r><w:t xml:space="preserve">. The solid-state storage controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve">, in the depicted embodiment, includes a configuration module </w:t></w:r><w:r><w:t>352</w:t></w:r><w:r><w:t xml:space="preserve"> that may be part of the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> and/or part of the read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve">, or may be independent from the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> and the read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve">. The components of the solid-state controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> and associated write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> and read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve"> are described below. In other embodiments, synchronous solid-state storage media </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t xml:space="preserve"> may be used and synchronization buffers </w:t></w:r><w:r><w:t>308</w:t></w:r><w:r><w:t>328</w:t></w:r><w:r><w:t xml:space="preserve"> may be eliminated.</w:t></w:r></w:p>
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