13189402

Paragraph Number

94

The solid-state storage controller 104 may also include control and status registers 340 and control queues 342, a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350. The solid-state storage controller 104, in the depicted embodiment, includes a configuration module 352 that may be part of the write data pipeline 106 and/or part of the read data pipeline 108, or may be independent from the write data pipeline 106 and the read data pipeline 108. The components of the solid-state controller 104 and associated write data pipeline 106 and read data pipeline 108 are described below. In other embodiments, synchronous solid-state storage media 110 may be used and synchronization buffers 308328 may be eliminated.

Added by DJM 3 2021