Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	US-8380915-A1	The solid-state storage media 110 is an array of non-volatile solid-state storage elements 216, 218, 220, arranged in banks 214, and accessed in parallel through a bi-directional storage input/output (“I/O”) bus 210. The storage I/O bus 210, in one embodiment, is capable of unidirectional communication at any one time. For example, when data is being written to the solid-state storage media 110, data cannot be read from the solid-state storage media 110. In another embodiment, data can flow both directions simultaneously. However bi-directional, as used herein with respect to a data bus, refers to a data pathway that can have data flowing in only one direction at a time, but when data flowing one direction on the bi-directional data bus is stopped, data can flow in the opposite direction on the bi-directional data bus.	54	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	A solid-state storage element (e.g. SSS 0.0216a) is typically configured as a chip (a package of one or more dies) or a die on a circuit board. As depicted, a solid-state storage element (e.g. 216a) operates independently or semi-independently of other solid-state storage elements (e.g. 218a) even if these several elements are packaged together in a chip package, a stack of chip packages, or some other package element. As depicted, a row of solid-state storage elements 216a, 216b, 216m is designated as a bank 214. As depicted, there may be “n” banks 214a-n and “m” solid-state storage elements 216a-m, 218a-m, 220a-m per bank in an array of n×m solid-state storage elements 216, 218, 220 in a solid-state storage media 110. Of course different embodiments may include different values for n and m. In one embodiment, the solid-state storage media 110a includes twenty solid-state storage elements 216, 218, 220 per bank 214 with eight banks 214. In one embodiment, the solid-state storage media 110a includes twenty four solid-state storage elements 216, 218, 220 per bank 214 with eight banks 214. In addition to the n×m storage elements 216, 218, 220, one or more additional columns (P) may also be addressed and operated in parallel with other solid-state storage elements 216a, 216b, 216m for one or more rows. The added P columns in one embodiment, store parity data for the portions of an ECC chunk (i.e. an ECC codeword) that span m storage elements for a particular bank. In one embodiment, each solid-state storage element 216, 218, 220 is comprised of single-level cell (“SLC”) devices. In another embodiment, each solid-state storage element 216, 218, 220 is comprised of multi-level cell (“MLC”) devices.	55	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, solid-state storage elements that share a common storage I/O bus 210a (e.g. 216b, 218b, 220b) are packaged together. In one embodiment, a solid-state storage element 216, 218, 220 may have one or more dies per chip with one or more chips stacked vertically and each die may be accessed independently. In another embodiment, a solid-state storage element (e.g. SSS 0.0216a) may have one or more virtual dies per die and one or more dies per chip and one or more chips stacked vertically and each virtual die may be accessed independently. In another embodiment, a solid-state storage element SSS 0.0216a may have one or more virtual dies per die and one or more dies per chip with some or all of the one or more dies stacked vertically and each virtual die may be accessed independently.	56	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, two dies are stacked vertically with four stacks per group to form eight storage elements (e.g. SSS 0.0-SSS 8.0) 216a-220a, each in a separate bank 214a-n. In another embodiment, 24 storage elements (e.g. SSS 0.0-SSS 0.24) 216 form a logical bank 214a so that each of the eight logical banks has 24 storage elements (e.g. SSS 0.0-SSS 8.24) 216, 218, 220. Data is sent to the solid-state storage media 110 over the storage I/O bus 210 to all storage elements of a particular group of storage elements (SSS 0.0-SSS 8.0) 216a, 218a, 220a. The storage control bus 212a is used to select a particular bank (e.g. Bank 0214a) so that the data received over the storage I/O bus 210 connected to all banks 214 is written just to the selected bank 214a.	57	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In certain embodiments, the storage control bus 212 and storage I/O bus 210 are used together by the solid-state controller 104 to communicate addressing information, storage element command information, and data to be stored. Those of skill in the art recognize that this address, data, and command information may be communicated using one or the other of these buses 212, 210, or using separate buses for each type of control information. In one embodiment, addressing information, storage element command information, and storage data travel on the storage I/O bus 210 and the storage control bus 212 carries signals for activating a bank as well as identifying whether the data on the storage I/O bus 210 lines constitute addressing information, storage element command information, or storage data.	58	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	For example, a control signal on the storage control bus 212 such as “command enable” may indicate that the data on the storage I/O bus 210 lines is a storage element command such as program, erase, reset, read, and the like. A control signal on the storage control bus 212 such as “address enable” may indicate that the data on the storage I/O bus 210 lines is addressing information such as erase block identifier, page identifier, and optionally offset within the page within a particular storage element. Finally, an absence of a control signal on the storage control bus 212 for both “command enable” and “address enable” may indicate that the data on the storage I/O bus 210 lines is storage data that is to be stored on the storage element at a previously addressed erase block, physical page, and optionally offset within the page of a particular storage element.	59	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the storage I/O bus 210 is comprised of one or more independent I/O buses (“IIOBa-m” comprising 210a.a-m, 210n.a-m) wherein the solid-state storage elements within each column share one of the independent I/O buses that accesses each solid-state storage element 216, 218, 220 in parallel so that all banks 214 are accessed simultaneously. For example, one channel of the storage I/O bus 210 may access a first solid-state storage element 216a, 218a, 220a of each bank 214a-n simultaneously. A second channel of the storage I/O bus 210 may access a second solid-state storage element 216b, 218b, 220b of each bank 214a-n simultaneously. Each row of solid-state storage element 216a, 216b, 216m is accessed simultaneously. In one embodiment, where solid-state storage elements 216, 218, 220 are multi-level (physically stacked), all physical levels of the solid-state storage elements 216, 218, 220 are accessed simultaneously. As used herein, “simultaneously” also includes near simultaneous access where devices are accessed at slightly different intervals to avoid switching noise. Simultaneously is used in this context to be distinguished from a sequential or serial access wherein commands and/or data are sent individually one after the other.	60	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Typically, banks 214a-n are independently selected using the storage control bus 212. In one embodiment, a bank 214 is selected using a chip enable or chip select. Where both chip select and chip enable are available, the storage control bus 212 may select one level of a multi-level solid-state storage element 216, 218, 220. In other embodiments, other commands are used by the storage control bus 212 to individually select one level of a multi-level solid-state storage element 216, 218, 220. Solid-state storage elements 216, 218, 220 may also be selected through a combination of control and of address information transmitted on storage I/O bus 210 and the storage control bus 212.	61	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, each solid-state storage element 216, 218, 220 is partitioned into erase blocks and each erase block is partitioned into pages. An erase block on a solid-state storage element 216, 218220 may be called a physical erase block or “PEB.” A typical page is 2000 bytes (“2 kB”). In one example, a solid-state storage element (e.g. SSS 0.0) includes two registers and can program two pages so that a two-register solid-state storage element 216, 218, 220 has a capacity of 4 kB. A bank 214 of 20 solid-state storage elements 216a, 216b, 216m would then have an 80 kB capacity of pages accessed with the same address going out the channels of the storage I/O bus 210.	62	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	This group of pages in a bank 214 of solid-state storage elements 216a, 216b, 216m of 80 kB may be called a logical page or virtual page. Similarly, an erase block of each storage element 216a-m of a bank 214a may be grouped to form a logical erase block or a virtual erase block. In one embodiment, an erase block of pages within a solid-state storage element 216, 218, 220 is erased when an erase command is received within a solid-state storage element 216, 218, 220. Whereas the size and number of erase blocks, pages, planes, or other logical and physical divisions within a solid-state storage element 216, 218, 220 are expected to change over time with advancements in technology, it is to be expected that many embodiments consistent with new configurations are possible and are consistent with the general description herein.	63	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Typically, when a packet is written to a particular location within a solid-state storage element 216, 218, 220, wherein the packet is intended to be written to a location within a particular page which is specific to a particular physical erase block of a particular storage element of a particular bank, a physical address is sent on the storage I/O bus 210 and followed by the packet. The physical address contains enough information for the solid-state storage element 216, 218, 220 to direct the packet to the designated location within the page. Since all storage elements in a column of storage elements (e.g. SSS 0.0-SSS N.0216a, 218a, 220a) are accessed simultaneously by the appropriate bus within the storage I/O bus 210a.a, to reach the proper page and to avoid writing the data packet to similarly addressed pages in the column of storage elements (SSS 0.0-SSS N.0216a, 218a, 220a), the bank 214a that includes the solid-state storage element SSS 0.0216a with the correct page where the data packet is to be written is simultaneously selected by the storage control bus 212.	64	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Similarly, satisfying a read command on the storage I/O bus 210 requires a simultaneous signal on the storage control bus 212 to select a single bank 214a and the appropriate page within that bank 214a. In one embodiment, a read command reads an entire page, and because there are multiple solid-state storage elements 216a, 216b, 216m in parallel in a bank 214, an entire logical page is read with a read command. However, the read command may be broken into subcommands, as will be explained below with respect to bank interleave. A logical page may also be accessed in a write operation.	65	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	An erase block erase command may be sent out to erase an erase block over the storage I/O bus 210 with a particular erase block address to erase a particular erase block. Typically, an erase block erase command may be sent over the parallel paths of the storage I/O bus 210 to erase a logical erase block, each with a particular erase block address to erase a particular erase block. Simultaneously a particular bank (e.g. Bank 0214a) is selected over the storage control bus 212 to prevent erasure of similarly addressed erase blocks in all of the banks (Banks 1-N 214b-n). Alternatively, no particular bank (e.g. Bank 0214a) is selected over the storage control bus 212 to enable erasure of similarly addressed erase blocks in all of the banks (Banks 1-N 214b-n) simultaneously. Other commands may also be sent to a particular location using a combination of the storage I/O bus 210 and the storage control bus 212. One of skill in the art will recognize other ways to select a particular storage location using the bi-directional storage I/O bus 210 and the storage control bus 212.	66	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, packets are written sequentially to the solid-state storage media 110. For example, packets are streamed to the storage write buffers of a bank 214a of storage elements 216 and when the buffers are full, the packets are programmed to a designated logical page. Packets then refill the storage write buffers and, when full, the packets are written to the next logical page. The next logical page may be in the same bank 214a or another bank (e.g. 214b). This process continues, logical page after logical page, typically until a logical erase block (“LEB”) is filled. In another embodiment, the streaming may continue across logical erase block boundaries with the process continuing, logical erase block after logical erase block.	67	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	As depicted, the bias module 318 biases the one or more packets prior to sending the packets to the ECC encoder 304. Depending on the method that the bias module 318 uses to bias the packets, and on other design considerations, in a further embodiment, the bias module 318 may receive data subsequent to the ECC encoder 304 in the write data pipeline 106, or be placed elsewhere in the write data pipeline 106. For example, in certain embodiments, it may be beneficial to keep ECC data separate from data that the bias module 318 biases, while in other embodiments it may be beneficial for the bias module 318 to bias data that includes ECC data from the ECC encoder 304.	115	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the write data pipeline 106 includes a garbage collector bypass 316 that receives data segments from the read data pipeline 108 as part of a data bypass in a garbage collection system. A garbage collection system typically marks packets that are no longer valid, typically because the packet is marked for deletion or has been modified and the modified data is stored in a different location. At some point, the garbage collection system determines that a particular section of storage may be recovered. This determination may be due to a lack of available storage capacity, the percentage of data marked as invalid reaching a threshold, a consolidation of valid data, an error detection rate for that section of storage reaching a threshold, or improving performance based on data distribution, etc. Numerous factors may be considered by a garbage collection algorithm to determine when a section of storage is to be recovered.	124	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the compression module 312 compresses a first segment with a first compression routine and passes along a second segment without compression. In another embodiment, the compression module 312 compresses a first segment with a first compression routine and compresses the second segment with a second compression routine. Having this flexibility within the solid-state storage device 102 is beneficial so that clients 114 or other devices writing data to the solid-state storage device 102 may each specify a compression routine or so that one can specify a compression routine while another specifies no compression. Selection of compression routines may also be selected according to default settings on a per data structure type or data structure class basis. For example, a first data structure of a specific data structure may be able to override default compression routine settings and a second data structure of the same data structure class and data structure type may use the default compression routine and a third data structure of the same data structure class and data structure type may use no compression.	123	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the write data pipeline 106 includes a compression module 312 that compresses the data for metadata segment prior to sending the data segment to the packetizer 302. The compression module 312 typically compresses a data or metadata segment using a compression routine known to those of skill in the art to reduce the storage size of the segment. For example, if a data segment includes a string of 512 zeros, the compression module 312 may replace the 512 zeros with code or token indicating the 512 zeros where the code is much more compact than the space taken by the 512 zeros.	122	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the encryption module 314 may encrypt the one or more packets using an encryption key unique to the solid-state storage device 102. The encryption module 314 may perform this media encryption independently, or in addition to the encryption described above. Typically, the entire packet is encrypted, including the headers. In another embodiment, headers are not encrypted. The media encryption by the encryption module 314 provides a level of security for data stored in the solid-state storage media 110. For example, where data is encrypted with media encryption unique to the specific solid-state storage device 102, if the solid-state storage media 110 is connected to a different solid-state storage controller 104, solid-state storage device 102, or computer 112, the contents of the solid-state storage media 110 typically could not be read without use of the same encryption key used during the write of the data to the solid-state storage media 110 without significant effort.	121	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the encryption module 314 encrypts a first packet with a first encryption key received in conjunction with the packet and encrypts a second packet with a second encryption key received in conjunction with the second packet. In another embodiment, the encryption module 314 encrypts a first packet with a first encryption key received in conjunction with the packet and passes a second data packet on to the next stage without encryption. Beneficially, the encryption module 314 included in the write data pipeline 106 of the solid-state storage device 102 allows data structure-by-data structure or segment-by-segment data encryption without a single file system or other external system to keep track of the different encryption keys used to store corresponding data structures or data segments. Each requesting device 155 or related key manager independently manages encryption keys used to encrypt only the data structures or data segments sent by the requesting device 155.	120	Added by DJM 3 2021	3/12/21, 12:00 AM

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