13189402

Paragraph Number

93

FIG. 3A is a schematic block diagram illustrating one embodiment 300 of a solid-state storage controller 104 with a write data pipeline 106 and a read data pipeline 108 in a solid-state storage device 102 in accordance with the present invention. The embodiment 300 includes a data bus 204, a local bus 206, and buffer control 208, which are substantially similar to those described in relation to the solid-state storage device controller 202 of FIG. 2. The write data pipeline 106 includes a packetizer 302 and an error-correcting code (“ECC”) encoder 304. In other embodiments, the write data pipeline 106 includes an input buffer 306, a write synchronization buffer 308, a write program module 310, a compression module 312, an encryption module 314, a garbage collector bypass 316 (with a portion within the read data pipeline 108), a bias module 318, and a write buffer 320. The read data pipeline 108 includes a read synchronization buffer 328, an ECC decoder 322, a depacketizer 324, an alignment module 326, and an output buffer 330. In other embodiments, the read data pipeline 108 may include an inverse bias module 332, a portion of the garbage collector bypass 316, a decryption module 334, a decompression module 336, and a read program module 338.

Added by DJM 3 2021