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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
93
Application Number
13189402
Reference Case 1
Reference Case 2
Content
FIG. 3A is a schematic block diagram illustrating one embodiment 300 of a solid-state storage controller 104 with a write data pipeline 106 and a read data pipeline 108 in a solid-state storage device 102 in accordance with the present invention. The embodiment 300 includes a data bus 204, a local bus 206, and buffer control 208, which are substantially similar to those described in relation to the solid-state storage device controller 202 of FIG. 2. The write data pipeline 106 includes a packetizer 302 and an error-correcting code (“ECC”) encoder 304. In other embodiments, the write data pipeline 106 includes an input buffer 306, a write synchronization buffer 308, a write program module 310, a compression module 312, an encryption module 314, a garbage collector bypass 316 (with a portion within the read data pipeline 108), a bias module 318, and a write buffer 320. The read data pipeline 108 includes a read synchronization buffer 328, an ECC decoder 322, a depacketizer 324, an alignment module 326, and an output buffer 330. In other embodiments, the read data pipeline 108 may include an inverse bias module 332, a portion of the garbage collector bypass 316, a decryption module 334, a decompression module 336, and a read program module 338.
Notes
Added by DJM 3 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody1"/></w:pPr><w:r><w:t>FIG. 3A</w:t></w:r><w:r><w:t xml:space="preserve"> is a schematic block diagram illustrating one embodiment </w:t></w:r><w:r><w:t>300</w:t></w:r><w:r><w:t xml:space="preserve"> of a solid-state storage controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> with a write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> and a read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve"> in a solid-state storage device </w:t></w:r><w:r><w:t>102</w:t></w:r><w:r><w:t xml:space="preserve"> in accordance with the present invention. The embodiment </w:t></w:r><w:r><w:t>300</w:t></w:r><w:r><w:t xml:space="preserve"> includes a data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">, a local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve">, and buffer control </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve">, which are substantially similar to those described in relation to the solid-state storage device controller </w:t></w:r><w:r><w:t>202</w:t></w:r><w:r><w:t xml:space="preserve"> of </w:t></w:r><w:r><w:t>FIG. 2</w:t></w:r><w:r><w:t xml:space="preserve">. The write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> includes a packetizer </w:t></w:r><w:r><w:t>302</w:t></w:r><w:r><w:t xml:space="preserve"> and an error-correcting code (“ECC”) encoder </w:t></w:r><w:r><w:t>304</w:t></w:r><w:r><w:t xml:space="preserve">. In other embodiments, the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> includes an input buffer </w:t></w:r><w:r><w:t>306</w:t></w:r><w:r><w:t xml:space="preserve">, a write synchronization buffer </w:t></w:r><w:r><w:t>308</w:t></w:r><w:r><w:t xml:space="preserve">, a write program module </w:t></w:r><w:r><w:t>310</w:t></w:r><w:r><w:t xml:space="preserve">, a compression module </w:t></w:r><w:r><w:t>312</w:t></w:r><w:r><w:t xml:space="preserve">, an encryption module </w:t></w:r><w:r><w:t>314</w:t></w:r><w:r><w:t xml:space="preserve">, a garbage collector bypass </w:t></w:r><w:r><w:t>316</w:t></w:r><w:r><w:t xml:space="preserve"> (with a portion within the read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve">), a bias module </w:t></w:r><w:r><w:t>318</w:t></w:r><w:r><w:t xml:space="preserve">, and a write buffer </w:t></w:r><w:r><w:t>320</w:t></w:r><w:r><w:t xml:space="preserve">. The read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve"> includes a read synchronization buffer </w:t></w:r><w:r><w:t>328</w:t></w:r><w:r><w:t xml:space="preserve">, an ECC decoder </w:t></w:r><w:r><w:t>322</w:t></w:r><w:r><w:t xml:space="preserve">, a depacketizer </w:t></w:r><w:r><w:t>324</w:t></w:r><w:r><w:t xml:space="preserve">, an alignment module </w:t></w:r><w:r><w:t>326</w:t></w:r><w:r><w:t xml:space="preserve">, and an output buffer </w:t></w:r><w:r><w:t>330</w:t></w:r><w:r><w:t xml:space="preserve">. In other embodiments, the read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve"> may include an inverse bias module </w:t></w:r><w:r><w:t>332</w:t></w:r><w:r><w:t xml:space="preserve">, a portion of the garbage collector bypass </w:t></w:r><w:r><w:t>316</w:t></w:r><w:r><w:t xml:space="preserve">, a decryption module </w:t></w:r><w:r><w:t>334</w:t></w:r><w:r><w:t xml:space="preserve">, a decompression module </w:t></w:r><w:r><w:t>336</w:t></w:r><w:r><w:t xml:space="preserve">, and a read program module </w:t></w:r><w:r><w:t>338</w:t></w:r><w:r><w:t>.</w:t></w:r></w:p>
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