16/146,238

Paragraph Number

90

Referring back to FIG. 3, the controller die 102 is shown as including the controller I/O circuitry 136, which is configured to send and receive signals communicated on the transmission lines 134, as previously described with respect to FIG. 2A. With respect to the configuration in FIG. 3, the controller I/O circuitry 136 is configured to send and receive signals communicated on the transmission line 308. For situations or embodiments where the controller 102 is to send a signal (e.g., a data signal, a clock signal, or a command signal) to the memory dies 304 via the transmission line 308, an output driver circuit of the controller I/O circuitry 136 generates and outputs the signal to the transmission line 308. In addition, for situations or embodiments where the controller 102 is to receive a signal from the memory dies 304 via the transmission line 308, an input circuit (e.g., an input buffer circuit) of the controller I/O circuitry 136 is configured to receive the signal from the transmission line 308.

Added by DJM 12 2021