16/146,238

Paragraph Number

91

Similarly, FIG. 3 shows each of the memory dies 304 as including respective memory I/O circuitry 158, as previously described with respect to FIG. 2B. For example, in FIG. 3, the first memory die 304(1) includes first memory I/O circuitry 158(1), the second memory die 304(2) includes second memory I/O circuitry 158(2), and the Nth memory die 304(N) includes Nth memory I/O circuitry 158(N). Each of the memory I/O circuitries 158 is configured to send and/or receive signals communicated on the transmission line 308. For situations or embodiments where a given kth memory die 304(k) is to send a signal (e.g., a data signal, a clock signal, or a command signal) to the controller die 102 via the transmission line 308, an output driver circuit of the kth memory I/O circuitry 158(k) generates and outputs the signal to the transmission line 308. In addition, for situations or embodiments where a given kth memory die 304(k) is to receive a signal from the controller die 102 via the transmission line 308, an input circuit (e.g., an input buffer circuit) of the kth memory I/O circuitry 158(k) is configured to receive the signal from the transmission line 308.

Added by DJM 12 2021