16869424
Paragraph Number139
6379
| Application | Calibrating non-volatile memory read thresholds | ||
|---|---|---|---|
| Matter Number | US10998041B1 | Reference Case 1 | US10998041B1 |
| Created | 12/22/21, 12:00 AM | Modified | 12/22/21, 12:00 AM |
Application Number
Content
In one embodiment, the LSB corresponds to a lower most page of data and the MSB corresponds to an upper most page of data, with the other two bits representing intermediate level pages of data. In certain embodiments, a multi-level storage cell may adhere to a multi-phase programming model, which includes writing the LSB before the intervening bits and MSB can be written or vice versa. In another embodiment, the LSB, intervening bits, and MSB may be programmed separately by the storage controller. Such an approach may be taken due to vendor or manufacturer requirements for page pairing (e.g., an LSB bit of MLC cell is paired with an MSB bit of a different MLC cell) and page addressing (e.g., LSB page is be programmed before the MSB page or vice versa). In certain instances, the LSB is written before the MSB is written, the MSB is written before the LSB is written, or the like.
Notes
Added by DJM 12 2021