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Delete 		ONSO3305US - Onsemi346 an active area comprised on the second side of the die; 68 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 a semiconductor die comprising a first side and a second side; 67 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 One or more side walls of the semiconductor die may be angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die. 12 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 A width of the scribe lines may be less than 150 microns. 26 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 The method may further include forming one or more dams on the first RDL. 25 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 The one or more sidewalls of the semiconductor die may be angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die after etching. 24 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 Etching the semiconductor wafer may include angling one or more sidewalls of the semiconductor wafer. 23 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 Implementations of methods of forming semiconductor packages may include one, all, or any of the following: 22 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 Implementations of semiconductor packages may be formed using implementations of methods for forming semiconductor package. Various method implementations may include: providing an optically transmissive substrate having a first side and a second side and forming a first redistribution layer (RDL) on a first side of the optically transmissive substrate. The first RDL may be formed over one or more scribe lines on the first side of the optically transmissive substrate. The method may also include providing a semiconductor wafer having a first side and a second side. A plurality of active areas may be on the second side of the semiconductor wafer and two or more die pads may be around each of the plurality of active areas. The method may include forming two or more inner bumps on each of the two or more die pads and coupling the second side of the semiconductor wafer to the first side of the optically transmissive substrate. The two or more inner bumps may be coupled on either side of the one or more scribe lines. The method may include thinning the semiconductor wafer to a predetermined thickness and etching the semiconductor wafer to the one or more scribe lines to form a plurality of semiconductor die. The method of forming semiconductor packages may also include singulating through each of the semiconductor die and a metal layer to expose one or more inner terminals of first RDL on the cover glass. The method may also include forming an isolation layer around each of the plurality of semiconductor die. The method may include forming a second redistribution layer (RDL). The second RDL may extend from the inner terminals of the first RDL to the first side of each of the plurality of semiconductor die. The method may include forming a passivation layer over the first side of each of the semiconductor die and singulating through the passivation layer and the optically transmissive substrate to form a plurality of semiconductor packages. 21 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 One or more sidewalls of the semiconductor die may be angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die. 20 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 The two or bumps may be coupled to two or more die pads. 15 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side. The semiconductor package may also include an active area on the second side of the die and two or more bumps coupled to a second side of the die on either side of the active area. A first redistribution layer (RDL) may be coupled to each of the two or more bumps and may extend to an edge of the semiconductor die. An optically transmissive lid may be coupled to the semiconductor die through the two or more bumps and the first RDL. The semiconductor package may also include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. 13 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 Each of the two or more die pads may have a pad pitch of substantially 60 microns. 27 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 The two or more bumps may include solder balls. 11 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 A pad pitch of the two or more bumps may be substantially 70 microns. 10 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 The two or more bumps may be copper pillars having solder tips. 9 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 A pad pitch of the two or more bumps may be substantially 60 microns. 8 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 Implementations of semiconductor packages may include one, all, or any of the following: 7 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die. 6 Added by DJM 3 2021 3/3/21, 12:00 AM
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Delete 		ONSO3305US - Onsemi346 Semiconductor packages sometimes have through silicon vias (TSVs) to provide electrical interconnection between front side metal pads and backside outer terminals of an image sensor package. Formation of TSVs includes silicon and dielectric etch, isolation lithography, as well as temperature changes during the processing steps. 5 Added by DJM 3 2021 3/3/21, 12:00 AM

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