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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
21
Application Number
16455676
Reference Case 1
Reference Case 2
Content
Implementations of semiconductor packages may be formed using implementations of methods for forming semiconductor package. Various method implementations may include: providing an optically transmissive substrate having a first side and a second side and forming a first redistribution layer (RDL) on a first side of the optically transmissive substrate. The first RDL may be formed over one or more scribe lines on the first side of the optically transmissive substrate. The method may also include providing a semiconductor wafer having a first side and a second side. A plurality of active areas may be on the second side of the semiconductor wafer and two or more die pads may be around each of the plurality of active areas. The method may include forming two or more inner bumps on each of the two or more die pads and coupling the second side of the semiconductor wafer to the first side of the optically transmissive substrate. The two or more inner bumps may be coupled on either side of the one or more scribe lines. The method may include thinning the semiconductor wafer to a predetermined thickness and etching the semiconductor wafer to the one or more scribe lines to form a plurality of semiconductor die. The method of forming semiconductor packages may also include singulating through each of the semiconductor die and a metal layer to expose one or more inner terminals of first RDL on the cover glass. The method may also include forming an isolation layer around each of the plurality of semiconductor die. The method may include forming a second redistribution layer (RDL). The second RDL may extend from the inner terminals of the first RDL to the first side of each of the plurality of semiconductor die. The method may include forming a passivation layer over the first side of each of the semiconductor die and singulating through the passivation layer and the optically transmissive substrate to form a plurality of semiconductor packages.
Notes
Added by DJM 3 2021
Raw Data
<w:p w14:paraId="21270B41" w14:textId="7AC5EC7A" w:rsidR="009802FF" w:rsidRDefault="009802FF" w:rsidP="009802FF"><w:pPr><w:numPr><w:ilvl w:val="0"/><w:numId w:val="7"/></w:numPr><w:overflowPunct w:val="0"/><w:autoSpaceDE w:val="0"/><w:autoSpaceDN w:val="0"/><w:adjustRightInd w:val="0"/><w:spacing w:line="480" w:lineRule="auto"/><w:rPr><w:szCs w:val="24"/></w:rPr></w:pPr><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>Implementations of semiconductor packages may be formed using implementations of methods for forming semiconductor package</w:t></w:r><w:r w:rsidR="004E3A4A"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>. Various method implementations</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> may include:</w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">providing an optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> substrate </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">having a first side and a second side and forming </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">a first redistribution layer (RDL) on a first side of the optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> substrate</w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>. T</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">he first RDL </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>may be formed</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> over one or more scribe lines on the first side of the optica</w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">lly </w:t></w:r><w:proofErr w:type="spellStart"/><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> substrate. The method may also include </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">providing a semiconductor wafer </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>having a first side and a second side. A</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> plurality of active areas </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>may be</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> on the second side of the semiconductor wafer and two or more die pads </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>may be</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> around each of the </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">plurality of active areas. The method may include </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>forming two or more inner bumps on each of the two or more die pads</w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> and </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">coupling the second side of the semiconductor wafer to </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:lastRenderedPageBreak/><w:t>the first side of the o</w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">ptically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> substrate. </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t>T</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">he two or more inner bumps </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">may be </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">coupled on either side </w:t></w:r><w:r><w:rPr><w:bCs/><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">of the one or more scribe lines. The method may include </w:t></w:r><w:r w:rsidRPr="009E651D"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>thinning the semiconductor wafer to a predetermined thickness</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> and </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>etching the semiconductor wafer to the one or more scribe lines to form a</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> plurality of semiconductor die. The method of forming semiconductor packages may also include </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>singulating through each of the semiconductor die and a metal layer to expose one or more inner terminals of first RDL on the cover glass</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">. The method may also include </w:t></w:r><w:r w:rsidRPr="009E651D"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>forming an isolation layer around each of the plurality of semicondu</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">ctor die. The method may include </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>forming a se</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>cond redistribution layer (RDL). T</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>he second RDL</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> may</w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> extend from the inner terminals of the first RDL to the first side of each of the</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> plurality of semiconductor die. The method may include </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>forming a passivation layer over the first side of eac</w:t></w:r><w:r><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">h of the semiconductor die and </w:t></w:r><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve">singulating through the passivation layer and the optically </w:t></w:r><w:proofErr w:type="spellStart"/><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t>transmissive</w:t></w:r><w:proofErr w:type="spellEnd"/><w:r w:rsidRPr="009802FF"><w:rPr><w:szCs w:val="24"/></w:rPr><w:t xml:space="preserve"> substrate to form a plurality of semiconductor packages.</w:t></w:r></w:p>
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