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This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended semiconductor packages will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such semiconductor packages, and implementing components and methods, consistent with the intended operation and methods. |
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DESCRIPTION |
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FIG. 18 is a cross sectional view of an implementation of a semiconductor package without through silicon vias (TSVs). |
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4.The semiconductor package of claim 3, wherein a pad pitch of the two or more bumps is substantially 70 microns. |
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9.The semiconductor package of claim 7, wherein a pad pitch of the two or more bumps is substantially 60 microns. |
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8.The semiconductor package of claim 7, wherein the two or bumps are coupled to two or more die pads. |
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a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die, the second RDL extending to the first side of the semiconductor die. |
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an optically transmissive lid coupled to the semiconductor die through the two or more bumps and the first RDL; |
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a first redistribution layer (RDL) coupled to each of the two or more bumps and extending to an edge of the semiconductor die; |
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two or more bumps coupled to a second side of the die on either side of the active area; |
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7.A semiconductor package comprising: |
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6.The semiconductor package of claim 1, wherein one or more side walls of the semiconductor die are angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die. |
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5.The semiconductor package of claim 1, wherein the two or more bumps comprise solder balls. |
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FIG. 17 is a side view of an implementation of semiconductor die coupled to an implementation of an optically transmissive substrate after formation of bumps on the first side of the semiconductor die; and |
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3.The semiconductor package of claim 1, wherein the two or more bumps are copper pillars comprising solder tips. |
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2.The semiconductor package of claim 1, wherein a pad pitch of the two or more bumps is substantially 60 microns. |
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wherein the first RDL extends to an edge of the semiconductor die. |
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a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die and extending to the first side of the semiconductor die; |
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an optically transmissive lid coupled to the semiconductor die through an adhesive, the two or more bumps, and a first redistribution layer (RDL); and |
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two or more bumps coupled to two or more die pads on a second side of the die; |
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