16869424
Paragraph Number79
6319
| Application | Calibrating non-volatile memory read thresholds | ||
|---|---|---|---|
| Matter Number | US10998041B1 | Reference Case 1 | US10998041B1 |
| Created | 12/22/21, 12:00 AM | Modified | 12/22/21, 12:00 AM |
Application Number
Content
The non-volatile memory array 206 is addressable by word line via a row decoder 210 and by bit line via a column decoder 212. "Word line" refers to a structure within a memory array comprising a set of memory cells. The memory array is configured such that the operational memory cells of the word line are read or sensed during a read operation. Similarly, the memory array is configured such that the operational memory cells of the word line are read, or sensed, during a read operation. A word line may also be referred to as a physical page or page for short. "Bit line" refers to a circuit structure configured to deliver a voltage and/or conduct current to a column of a memory array. In one embodiment, the column comprises a NAND string or memory string and may also be referred to as channel. In one embodiment, the column is referred to as a NAND string and the NAND string comprises a channel. In one embodiment, a bit line connects to a NAND string at a drain end or drain side of the NAND string. A memory array may have one bit line for each memory cell along the word lines of the memory array.
Notes
Added by DJM 12 2021