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"Erase block" refers to a logical erase block or a physical erase block. In one embodiment, a physical erase block represents the smallest storage unit within a given memory die that can be erased at a given time (e.g., due to the wiring of storage cells on the memory die). In one embodiment, logical erase blocks represent the smallest storage unit, or storage block, erasable by a storage controller in response to receiving an erase command. In such an embodiment, when the storage controller receives an erase command specifying a particular logical erase block, the storage controller may erase each physical erase block within the logical erase block simultaneously. It is noted that physical erase blocks within a given logical erase block may be considered as contiguous within a physical address space even though they reside in separate dies. Thus, the term "contiguous" may be applicable not only to data stored within the same physical medium, but also to data stored within separate media. |
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Therefore, in some embodiments, the storage controller 102 may be configured to write data out-of-place. As used herein, writing data "out-of-place" refers to writing data to different media storage location(s) rather than overwriting the data "in-place" (e.g., overwriting the original physical location of the data). Modifying data out-of-place may avoid write amplification, since existing, valid data on the erase block with the data to be modified need not be erased and recopied. Moreover, writing data out-of-place may remove erasure from the latency path of many storage operations (e.g., the erasure latency is no longer part of the critical path of a write operation). "Storage operation" refers to an operation performed on a memory cell in order to change, or obtain, the value of data represented by a state characteristic of the memory cell. Examples of storage operations include but are not limited to reading data from (or sensing a state of) a memory cell, writing (or programming) data to a memory cell, and/or erasing data stored in a memory cell. |
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Management of a data block by a storage manager includes specifically addressing a particular data block for a read operation, write operation, or maintenance operation. "Maintenance operation" refers to an operation performed on a non-volatile storage device that is configured, designed, calibrated, or arranged to improve or extend the life of the non-volatile storage device and/or data stored thereon. |
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In conventional block storage devices, a logical address maps directly to a particular data block on physical storage media. In conventional block storage devices, each data block maps to a particular set of physical sectors on the physical storage media. However, certain storage devices do not directly or necessarily associate logical addresses with particular physical data blocks. These storage devices may emulate a conventional block storage interface to maintain compatibility with a block storage client 110. |
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In one embodiment, the storage controller 102 provides a block I/O emulation layer, which serves as a block device interface, or API. In this embodiment, the storage client 110 communicates with the storage device through this block device interface. In one embodiment, the block I/O emulation layer receives commands and logical addresses from the storage client 110 in accordance with this block device interface. As a result, the block I/O emulation layer provides the storage device compatibility with a block storage client 110. |
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In one embodiment, a storage client 110 communicates with the storage controller 102 through a host interface comprising a direct interface. In this embodiment, the storage device directly exchanges information specific to non-volatile storage devices. "Non-volatile storage device" refers to any hardware, device, component, element, or circuit configured to maintain an alterable physical characteristic used to represent a binary value of zero or one after a primary power source is removed. Examples of a non-volatile storage device include, but are not limited to, a hard disk drive (HDD), Solid-State Drive (SSD), non-volatile memory media, and the like. |
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A storage device using direct interface may store data in the memory die 104 using a variety of organizational constructs including, but not limited to, blocks, sectors, pages, logical blocks, logical pages, erase blocks, logical erase blocks, ECC codewords, logical ECC codewords, or in any other format or structure advantageous to the technical characteristics of the memory die 104. "Characteristic" refers to any property, trait, quality, or attribute of an object or thing. Examples of characteristics include, but are not limited to, condition, readiness for use, unreadiness for use, size, weight, composition, feature set, and the like. |
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The storage controller 102 receives a logical address and a command from the storage client 110 and performs the corresponding operation in relation to the memory die 104. The storage controller 102 may support block I/O emulation, a direct interface, or both. |
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FIG. 2 is a block diagram of an exemplary storage device 200. "Storage device" refers to any hardware, system, sub-system, circuit, component, module, non-volatile memory media, hard disk drive, storage array, device, or apparatus configured, programmed, designed, or engineered to store data for a period of time and retain the data in the storage device while the storage device is not using power from a power supply. Examples of storage devices include, but are not limited to, a hard disk drive, FLASH memory, MRAM memory, a Solid-State storage device, Just a Bunch Of Disks (JBOD), Just a Bunch Of Flash (JBOF), an external hard disk, an internal hard disk, and the like. |
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The storage device 200 may include a storage controller 102 and a memory array 202. Each memory die 104 in the memory array 202 may include a die controller 204, at least one non-volatile memory array 206 in the form of a three-dimensional array, and read/write circuits 208. |
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"Three-dimensional memory array" refers to a physical arrangement of components of a memory array which contrasts with a two-dimensional (2-D) memory array. 2-D memory arrays are formed along a planar surface of a semiconductor wafer or other substrate. A three-dimensional (3-D) memory array extends up from the wafer surface/substrate and generally includes stacks, or columns, of memory cells extending upwards, in a z-direction. In a 3-D memory array word lines comprise layers stacked one on the other as the memory array extends upwards. Various 3-D arrangements are possible. In one arrangement a NAND string is formed vertically with one end (e.g., source) at the wafer surface and the other end (e.g., drain) on top. |
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"Threshold voltage" refers to a voltage level that when applied to a gate terminal of a transistor causes the transistor to conduct a current between the drain electrode and source electrode. |
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Consequently, a non-volatile memory array is a memory array having memory cells configured such that a characteristic (e.g., threshold voltage level, resistance level, conductivity, etc.) of the memory cell used to represent stored data remains a property of the memory cell without a requirement for using a power source to maintain the characteristic. |
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A memory array is addressable using a row identifier and a column identifier. Those of skill in the art recognize that a memory array may comprise the set of memory cells within a plane, the set of memory cells within a memory die, the set of memory cells within a set of planes, the set of memory cells within a set of memory die, the set of memory cells within a memory package, the set of memory cells within a set of memory packages, or with other known memory cell set architectures and configurations. |
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A memory array may include a set of memory cells at a number of levels of organization within a storage or memory system. In one embodiment, memory cells within a plane may be organized into a memory array. In one embodiment, memory cells within a plurality of planes of a memory die may be organized into a memory array. In one embodiment, memory cells within a plurality of memory dies of a memory device may be organized into a memory array. In one embodiment, memory cells within a plurality of memory devices of a storage system may be organized into a memory array. |
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The non-volatile memory array 206 is addressable by word line via a row decoder 210 and by bit line via a column decoder 212. "Word line" refers to a structure within a memory array comprising a set of memory cells. The memory array is configured such that the operational memory cells of the word line are read or sensed during a read operation. Similarly, the memory array is configured such that the operational memory cells of the word line are read, or sensed, during a read operation. A word line may also be referred to as a physical page or page for short. "Bit line" refers to a circuit structure configured to deliver a voltage and/or conduct current to a column of a memory array. In one embodiment, the column comprises a NAND string or memory string and may also be referred to as channel. In one embodiment, the column is referred to as a NAND string and the NAND string comprises a channel. In one embodiment, a bit line connects to a NAND string at a drain end or drain side of the NAND string. A memory array may have one bit line for each memory cell along the word lines of the memory array. |
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"Channel" refers to a structure within a memory array that extends from a source side to a drain side. In one embodiment, a channel is a vertical column within a memory array that forms a conductive path between a source line coupled to one end of a NAND string and a bit line coupled to another end of the NAND string. A channel may be formed from a variety of materials including, for example, polysilicon. |
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In one embodiment, a channel within a NAND string creates a conductive path by activating one or more memory cells (e.g., one or more selected memory cells and unselected memory cells) along the NAND string, and one or more control structures (e.g., select gates (source and/or drain) between a source line connected to one end (e.g., the source side) of the NAND string and a sense amplifier or bit line connected to the other end (e.g., the drain side) of the NAND string. |
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"Select gate" refers to a transistor structurally and/or electrically configured to function as a switch to electrically connect a first electrical structure connected to a source terminal of the transistor to a second electrical structure connected to the drain terminal. When functioning as a switch, the transistor is referred to herein as a `select gate` and serves to gate (selectively) or control when, and in what quantity, a current flows or a voltage passes between the first electrical structure and the second electrical structure. Depending on the context, references to select gate herein may refer to the whole transistor or to the gate terminal of the transistor. |
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The read/write circuits 208 include multiple sense blocks SB1, SB2, . . . , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. In certain embodiments, each memory cell across a row of the memory array together form a physical page. "Read/write circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured and/or operational to read data from and write data to a storage media, such as storage cells of a storage array. |
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