16869424
Paragraph Number74
6314
| Application | Calibrating non-volatile memory read thresholds | ||
|---|---|---|---|
| Matter Number | US10998041B1 | Reference Case 1 | US10998041B1 |
| Created | 12/22/21, 12:00 AM | Modified | 12/22/21, 12:00 AM |
"Three-dimensional memory array" refers to a physical arrangement of components of a memory array which contrasts with a two-dimensional (2-D) memory array. 2-D memory arrays are formed along a planar surface of a semiconductor wafer or other substrate. A three-dimensional (3-D) memory array extends up from the wafer surface/substrate and generally includes stacks, or columns, of memory cells extending upwards, in a z-direction. In a 3-D memory array word lines comprise layers stacked one on the other as the memory array extends upwards. Various 3-D arrangements are possible. In one arrangement a NAND string is formed vertically with one end (e.g., source) at the wafer surface and the other end (e.g., drain) on top.
Added by DJM 12 2021