Paragraph 44

Paragraph 44

Application: FSP1845

Matter Number FSP1845
Paragraph Number 44
Application Number 16/146,238
Reference Case 1 FSP1845
Reference Case 2
Created 12/22/21, 12:00 AM
Modified 12/22/21, 12:00 AM
Id 6,557
Content
The controller die 102 may include a buffer manager/bus controller module 114 that manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration for communication on an internal communications bus 117 of the controller die 102. A read only memory (ROM) 118 may store and/or access system boot code. Although illustrated in FIG. 2A as located separately from the controller die 102, in other embodiments one or both of the RAM 116 and the ROM 118 may be located within the controller die 102. In yet other embodiments, portions of RAM 116 and ROM 118 may be located both within the controller die 102 and outside the controller die 102. Further, in some implementations, the controller die 102, the RAM 116, and the ROM 118 may be located on separate semiconductor dies.
Notes Added by DJM 12 2021