Paragraph 103
Paragraph 103
Application
Calibrating non-volatile memory read thresholds
Matter Number
US10998041B1
Paragraph Number
103
Application Number
16869424
Reference Case 1
US10998041B1
Reference Case 2
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Created
12/22/21, 12:00 AM
Modified
12/22/21, 12:00 AM
Id
6,343
Content
FIG. 3 illustrates a memory array 300 in accordance with one embodiment. In the illustrated embodiment, memory array 300 is organized into logical erase blocks (LEBs), as shown by logical erase block 302 (also referred to herein as a "metablock" or "superblock"). These LEBs include multiple physical erase blocks (PEBs) illustrated by physical erase block 0 304, physical erase block n 306, physical erase block 0 308, physical erase block n 310, physical erase block 0 312, and physical erase block n 314. "Physical erase block" refers to smallest storage unit within a given memory die that can be erased at a given time (e.g., due to the wiring of storage cells on the memory die).
Notes
Added by DJM 12 2021