Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	US-8380915-A1	In one embodiment, the storage cells in the storage elements 216, 218, 220 in an empty or erased state store initial binary values. The initial binary values represent a bias for the storage cells. For example, the storage cells may have a physical, electrical, mechanical, or other quality that causes them to store a certain value by default. In another embodiment, the bias may be intentionally selected based on design considerations of the solid-state storage media 110, on security considerations, on compatibility issues, or the like, and may not be based on a default property of the storage cells.	106	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Each of the storage elements 216, 218, 220, in one embodiment, store binary data in a plurality of storage cells that exhibit a bias. Each storage cell stores one or more binary bits, or values. Flash memory storage cells may be single-level cells (“SLC”) that each store a single binary bit, or multi-level cells (“MLC”) that each store two or more binary bits. Examples of storage cells include transistors, capacitors, magnetic elements, mechanical elements, optical elements, and the like. In flash memory, each storage cell is typically a floating-gate transistor. NRAM, MRAM, DRAM, PRAM, and other types of solid-state storage may have other types of storage cells, and may store either a single binary bit or two or more binary bits per storage cell.	105	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	For example, in one embodiment, end sections of data files may be padded with binary zeroes, causing the data packets that store the end sections to exhibit a bias toward binary zeroes, meaning that the data packets have more binary zeroes than binary ones. Other data packets may have more binary ones than zeroes, or a balance of binary ones and zeroes. While data packets may each have an individual bias based on data within the packets, a bias of the storage cells of the solid-state storage media 110 may be based on some benefit associated with the storage of a particular binary value or pattern, or some property of the storage cells. One example of a storage cell property, NAND flash storage cells presently are biased to all binary one values or almost all binary one values when provided by a manufacturer. In addition, performing an erase operation on the NAND flash storage cells sets the binary values in each storage cell to a binary one, such that programming of the storage cells comprises changing certain storage cells to a binary zero value. This bias to all binary one values or almost all binary one values when provided by a manufacturer or when erased represents one example of an empty state for storage cells of a non-volatile solid-state storage media.	104	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the write data pipeline 106 also includes a bias module 318 that receives the one or more packets from the packetizer 302, either directly or indirectly. The bias module 318 biases the bits of the data packets toward a bias of storage cells of the solid-state storage media 110. As used herein, a “bias” is a preference, probability, tendency, or desirability of values for bits within a set of bits to exhibit a specific data pattern. A bias may be a natural property, a designed attribute, a property of performing an operation on storage media, or a random occurrence. Data itself may have a bias and data storage media may have a bias. A bias may be toward binary ones, toward binary zeroes, toward a balance of binary ones and zeroes, toward a certain binary value for certain bits, or the like.	103	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The bias module 318 biases a packet by changing a bias of the packet to more closely match a bias of the storage cells of the solid-state storage media 110. The bias module 318 biases the packets in a reversible manner, such that the inverse bias module 332 can convert the packets back to their original source data values with their original source biases. In one embodiment, the packets that the bias module 318 biases are sized for storage in a specific logical or physical storage region or division of the solid-state storage media 110, such as an erase block, a virtual erase block, a page, a virtual page, an ECC chunk, a division within a page, or the like. In one embodiment, the bias module 318 selectively biases certain packets based on a bias of the packets, and may not bias other packets.	112	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the write pipeline 106 includes an input buffer 306 that receives a data segment to be written to the solid-state storage media 110 and stores the incoming data segments until the next stage of the write data pipeline 106, such as the packetizer 302 (or other stage for a more complex write data pipeline 106) is ready to process the next data segment. The input buffer 306 typically allows for discrepancies between the rate data segments are received and processed by the write data pipeline 106 using an appropriately sized data buffer. The input buffer 306 also allows the data bus 204 to transfer data to the write data pipeline 106 at rates greater than can be sustained by the write data pipeline 106 in order to improve efficiency of operation of the data bus 204. Typically when the write data pipeline 106 does not include an input buffer 306, a buffering function is performed elsewhere, such as in the solid-state storage device 102 but outside the write data pipeline 106, in the computer 112, such as within a network interface card (“NIC”), or at another device, for example when using remote direct memory access (“RDMA”).	101	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Beneficially, using a robust ECC algorithm allowing more than single bit correction or even double bit correction allows the life of the solid-state storage media 110 to be extended. For example, if flash memory is used as the storage medium in the solid-state storage media 110, the flash memory may be written approximately 100,000 times without error per erase cycle. This usage limit may be extended using a robust ECC algorithm. Having the ECC encoder 304 and corresponding ECC decoder 322 onboard the solid-state storage device 102, the solid-state storage device 102 can internally correct errors and has a longer useful life than if a less robust ECC algorithm is used, such as single bit correction. However, in other embodiments the ECC encoder 304 may use a less robust algorithm and may correct single-bit or double-bit errors. In another embodiment, the solid-state storage media 110 may comprise less reliable storage such as multi-level cell (“MLC”) flash in order to increase capacity, which storage may not be sufficiently reliable without more robust ECC algorithms.	100	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The write data pipeline 106 includes an ECC encoder 304 that that generates one or more error-correcting codes (“ECC”) for the one or more packets received from the packetizer 302. The ECC encoder 304 typically uses an error correcting algorithm to generate ECC check bits which are stored with the one or more data packets. The ECC codes generated by the ECC encoder 304 together with the one or more data packets associated with the ECC codes comprise an ECC chunk. The ECC data stored with the one or more data packets is used to detect and to correct errors introduced into the data through transmission and storage. In one embodiment, packets are streamed into the ECC encoder 304 as un-encoded blocks of length N. A syndrome of length S is calculated, appended and output as an encoded block of length N+S. The value of N and S are dependent upon the characteristics of the algorithm which is selected to achieve specific performance, efficiency, and robustness metrics. In one embodiment, there is no fixed relationship between the ECC blocks and the packets; the packet may comprise more than one ECC block; the ECC block may comprise more than one packet; and a first packet may end anywhere within the ECC block and a second packet may begin after the end of the first packet within the same ECC block. In one embodiment, ECC algorithms are not dynamically modified. In one embodiment, the ECC data stored with the data packets is robust enough to correct errors in more than two bits.	99	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Each packet includes a header and possibly data from the data or metadata segment. The header of each packet includes pertinent information to relate the packet to the data structure to which the packet belongs. For example, the header may include an object identifier or other data structure identifier and offset that indicates the data segment, object, data structure or data block from which the data packet was formed. The header may also include a logical address used by the storage bus controller 348 to store the packet. The header may also include information regarding the size of the packet, such as the number of bytes included in the packet. The header may also include a sequence number that identifies where the data segment belongs with respect to other packets within the data structure when reconstructing the data segment or data structure. The header may include a header type field. Type fields may include data, data structure attributes, metadata, data segment delimiters (multi-packet), data structure types, data structure linkages, and the like. One of skill in the art will recognize other information that may be included in a header added to data or metadata by a packetizer 302 and other information that may be added to a packet.	98	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Each data structure is stored as one or more packets. Each data structure may have one or more container packets. Each packet contains a header. The header may include a header type field. Type fields may include data, attribute, metadata, data segment delimiters (multi-packet), data structures, data linkages, and the like. The header may also include information regarding the size of the packet, such as the number of bytes of data included in the packet. The length of the packet may be established by the packet type. The header may include information that establishes the relationship of the packet to a data structure. An example might be the use of an offset in a data packet header to identify the location of the data segment within the data structure. One of skill in the art will recognize other information that may be included in a header added to data by a packetizer 302 and other information that may be added to a data packet.	97	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The write data pipeline 106 includes a packetizer 302 that receives a data or metadata segment to be written to the solid-state storage, either directly or indirectly through another write data pipeline 106 stage, and creates one or more packets sized for the solid-state storage media 110. The data or metadata segment is typically part of a data structure such as an object, but may also include an entire data structure. In another embodiment, the data segment is part of a block of data, but may also include an entire block of data. Typically, a set of data such as a data structure is received from a computer 112, client 114, or other computer or device and is transmitted to the solid-state storage device 102 in data segments streamed to the solid-state storage device 102 or computer 112. A data segment may also be known by another name, such as data parcel, but as referenced herein includes all or a portion of a data structure or data block.	96	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Write Data Pipeline	95	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The solid-state storage controller 104 may also include control and status registers 340 and control queues 342, a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350. The solid-state storage controller 104, in the depicted embodiment, includes a configuration module 352 that may be part of the write data pipeline 106 and/or part of the read data pipeline 108, or may be independent from the write data pipeline 106 and the read data pipeline 108. The components of the solid-state controller 104 and associated write data pipeline 106 and read data pipeline 108 are described below. In other embodiments, synchronous solid-state storage media 110 may be used and synchronization buffers 308328 may be eliminated.	94	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the encryption module 314 may encrypt the one or more packets using an encryption key unique to the solid-state storage device 102. The encryption module 314 may perform this media encryption independently, or in addition to the encryption described above. Typically, the entire packet is encrypted, including the headers. In another embodiment, headers are not encrypted. The media encryption by the encryption module 314 provides a level of security for data stored in the solid-state storage media 110. For example, where data is encrypted with media encryption unique to the specific solid-state storage device 102, if the solid-state storage media 110 is connected to a different solid-state storage controller 104, solid-state storage device 102, or computer 112, the contents of the solid-state storage media 110 typically could not be read without use of the same encryption key used during the write of the data to the solid-state storage media 110 without significant effort.	121	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	For depicted embodiment with a write buffer 320 sized larger than a virtual page, a single write command, which includes numerous subcommands, can then be followed by a single program command to transfer the page of data from the storage write buffer in each solid-state storage element 216, 218, 220 to the designated page within each solid-state storage element 216, 218, 220. This technique has the benefits of eliminating partial page programming, which is known to reduce data reliability and durability and freeing up the destination bank for reads and other commands while the buffer fills.	129	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	While the write buffer 320 is being filled, the solid-state storage media 110 may be used for other read operations. This is advantageous because other solid-state devices with a smaller write buffer or no write buffer may tie up the solid-state storage when data is written to a storage write buffer and data flowing into the storage write buffer stalls. Read operations will be blocked until the entire storage write buffer is filled and programmed. Another approach for systems without a write buffer or a small write buffer is to flush the storage write buffer that is not full in order to enable reads. Again this is inefficient because multiple write/program cycles are required to fill a page.	128	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the write data pipeline 106 includes a write buffer 320 that buffers data for efficient write operations. Typically, the write buffer 320 includes enough capacity for packets to fill at least one virtual page in the solid-state storage media 110. This allows a write operation to send an entire page of data to the solid-state storage media 110 without interruption. By sizing the write buffer 320 of the write data pipeline 106 and buffers within the read data pipeline 108 to be the same capacity or larger than a storage write buffer within the solid-state storage media 110, writing and reading data is more efficient since a single write command may be crafted to send a full virtual page of data to the solid-state storage media 110 instead of multiple commands.	127	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The garbage collector bypass 316 coordinates insertion of segments into the write data pipeline 106 with other segments being written by clients 114 or other devices. In the depicted embodiment, the garbage collector bypass 316 is before the packetizer 302 in the write data pipeline 106 and after the depacketizer 324 in the read data pipeline 108, but may also be located elsewhere in the read and write data pipelines 106, 108. The garbage collector bypass 316 may be used during a flush of the write pipeline 108 to fill the remainder of the virtual page in order to improve the efficiency of storage within the solid-state storage media 110 and thereby reduce the frequency of garbage collection.	126	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Once a section of storage has been marked for recovery, valid packets in the section typically must be relocated. The garbage collector bypass 316 allows packets to be read into the read data pipeline 108 and then transferred directly to the write data pipeline 106 without being routed out of the solid-state storage controller 104. In one embodiment, the garbage collector bypass 316 is part of an autonomous garbage collector system that operates within the solid-state storage device 102. This allows the solid-state storage device 102 to manage data so that data is systematically spread throughout the solid-state storage media 110 to improve performance, data reliability and to avoid overuse and underuse of any one location or area of the solid-state storage media 110 and to lengthen the useful life of the solid-state storage media 110.	125	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the write data pipeline 106 includes a garbage collector bypass 316 that receives data segments from the read data pipeline 108 as part of a data bypass in a garbage collection system. A garbage collection system typically marks packets that are no longer valid, typically because the packet is marked for deletion or has been modified and the modified data is stored in a different location. At some point, the garbage collection system determines that a particular section of storage may be recovered. This determination may be due to a lack of available storage capacity, the percentage of data marked as invalid reaching a threshold, a consolidation of valid data, an error detection rate for that section of storage reaching a threshold, or improving performance based on data distribution, etc. Numerous factors may be considered by a garbage collection algorithm to determine when a section of storage is to be recovered.	124	Added by DJM 3 2021	3/12/21, 12:00 AM

Page 12 of 17, showing 20 record(s) out of 335 total